ISP1507EBS,518 NXP Semiconductors, ISP1507EBS,518 Datasheet - Page 53

• Manufacturer Part Number: ISP1507EBS,518
• Description: RF Transceiver USB 2.0 ULPI TRNSCVR
• Manufacturer: NXP Semiconductors

Specifications of ISP1507EBS,518

• Number Of Transceivers: 1
• Esd Protection: YeskV
• Power Supply Requirement: Single
• Operating Supply Voltage (typ): 3.3V
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Dual Supply Voltage (typ): Not RequiredV
• Dual Supply Voltage (max): Not RequiredV
• Dual Supply Voltage (min): Not RequiredV
• Mounting: Surface Mount
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Lead Free Status / RoHS Status: Compliant
• Other names: 935285498518 ISP1507EBS-T

NXP Semiconductors
Table 41.
Table 42.
ISP1507E_ISP1507F_1
Product data sheet
Bit
Symbol
Reset
Access
Bit
7 to 4 -
3
2
1
0
Symbol
BVALID_FALL
BVALID_RISE
reserved
IGNORE_RESET
PWR_CTRL - Power Control register (address R = 3Dh to 3Fh, W = 3Dh, S = 3Eh, C = 3Fh) bit allocation
PWR_CTRL - Power Control register (address R = 3Dh to 3Fh, W = 3Dh, S = 3Eh, C = 3Fh) bit description
10.1.11 Reserved
10.1.12 Access extended register set
10.1.13 Vendor-specific registers
10.1.14 PWR_CTRL register
R/W/S/C
10.2 Extended register set
7
0
Registers 19h to 2Eh are not implemented. Operating on these addresses will have no
effect on the PHY.
Address 2Fh does not contain register data. Instead it links to the extended register set.
The immediate register set maps to the lower end of the extended register set.
Addresses 30h to 3Fh contain vendor-specific registers.
This register controls various aspects of the ISP1507.
the register.
Addresses 00h to 3Fh of the extended register set directly map to the immediate set. This
means a read, write, set or clear operation to these extended addresses will operate on
the immediate register set.
Addresses 40h to FFh are not implemented. Operating on these addresses may result in
undefined behavior of the PHY.
Description
reserved; the link must never write logic 1 to these bits
BVALID Fall: Enables RXCMDs for HIGH-to-LOW transitions on BVALID. When BVALID
changes from HIGH to LOW, the ISP1507 will send an RXCMD to the link with the ALT_INT bit
set to logic 1.
This bit is optional and is not necessary for OTG devices. This bit is provided for debugging
purposes. The session valid comparator must be used instead.
BVALID Rise: Enables RXCMDs for LOW-to-HIGH transitions on BVALID. When BVALID
changes from LOW to HIGH, the ISP1507 will send an RXCMD to the link with the ALT_INT bit
set to logic 1.
This bit is optional and is not necessary for OTG devices. This bit is provided for debugging
purposes. The session valid comparator must be used instead.
-
Ignore Reset: Selects between the RESET_N and PSW_N functions of the RESET_N/PSW_N
pin. The link must set this bit to logic 1 if PSW_N is used in a ganged mode configuration.
0b — The RESET_N/PSW_N pin behaves as an active-LOW reset input (RESET_N) (default).
1b — The RESET_N/PSW_N pin behaves as an active-LOW power switch output (PSW_N).
R/W/S/C
6
0
reserved
R/W/S/C
5
0
Rev. 01 — 28 May 2008
R/W/S/C
4
0
BVALID_
R/W/S/C
FALL
3
0
ISP1507E; ISP1507F
Table 41
BVALID_
R/W/S/C
RISE
ULPI HS USB OTG transceiver
2
0
shows the bit allocation of
reserved
R/W/S/C
1
0
© NXP B.V. 2008. All rights reserved.
IGNORE_
R/W/S/C
RESET
0
0
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