ISP1507EBS,518 NXP Semiconductors, ISP1507EBS,518 Datasheet - Page 21

• Manufacturer Part Number: ISP1507EBS,518
• Description: RF Transceiver USB 2.0 ULPI TRNSCVR
• Manufacturer: NXP Semiconductors

Specifications of ISP1507EBS,518

• Number Of Transceivers: 1
• Esd Protection: YeskV
• Power Supply Requirement: Single
• Operating Supply Voltage (typ): 3.3V
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Dual Supply Voltage (typ): Not RequiredV
• Dual Supply Voltage (max): Not RequiredV
• Dual Supply Voltage (min): Not RequiredV
• Mounting: Surface Mount
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Lead Free Status / RoHS Status: Compliant
• Other names: 935285498518 ISP1507EBS-T

NXP Semiconductors
9. Protocol description
ISP1507E_ISP1507F_1
Product data sheet
9.1 ULPI references
9.2 Power-On Reset (POR)
9.3 Power-up, reset and bus idle sequence
The following subsections describe the protocol for using the ISP1507.
Remark: In all figures, the ULPI data is shown in a generic form and not as nibbles on the
rising and falling edges of the clock.
The ISP1507 provides an 8-pin ULPI to communicate with the link. It is highly
recommended that you read UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1 and
UTMI+ Specification Rev. 1.0 .
An internal POR is generated when REG1V8 rises above V
t
below V
voltage on REG1V8 is generated from V
To give a better view of the functionality,
internal POR starts with logic 0 at t0. At t1, the detector will see the passing of the trip
level so that POR turns to logic 1 and a delay element will add another t
drops to logic 0. If REG1V8 dips from t2 to t3 for > t
generated. If the dip at t4 to t5 is too short, that is, < t
will not react and will remain LOW.
Figure 6
On power-up, the ISP1507 performs an internal power-on reset and asserts DIR to
indicate to the link that the ULPI bus cannot be used. When the internal PLL is stable, the
ISP1507 deasserts DIR. The power-up time depends on the V
crystal start-up time, and PLL start-up time t
the ISP1507 drives the NXT pin to LOW and drives DATA[3:0] with RXCMD values. When
DIR is deasserted, the link must drive the data bus to a valid level. By default, the link
must drive data to LOW. When the ISP1507 initially deasserts DIR on power-up, the link
must ignore all RXCMDs until it resets the ISP1507. Before beginning USB packets, the
link must set the RESET bit in the FUNC_CTRL register (see
ISP1507. After the RESET bit is set, the ISP1507 will assert DIR until the internal reset
completes. The ISP1507 will automatically deassert DIR and clear the RESET bit when
w(REG1V8_H)
Fig 5.
POR(trip)
shows a typical start-up sequence.
Internal power-on reset timing
t0
. The internal POR pulse will also be generated whenever REG1V8 drops
for more than t
t1
t
PORP
Rev. 01 — 28 May 2008
w(REG1V8_L)
t2
Figure 5
CC
, and then rises above V
.
startup(o)(CLOCK)
t3
ISP1507E; ISP1507F
t
PORP
shows a possible curve of REG1V8. The
w(REG1V8_L)
w(REG1V8_L)
t4
ULPI HS USB OTG transceiver
. Whenever DIR is asserted,
POR(trip)
t5
Section
CC
, another POR pulse is
, the internal POR pulse
supply rise time, the
POR(trip)
, for at least
10.1.2) to reset the
© NXP B.V. 2008. All rights reserved.
004aaa751
PORP
REG1V8
V
POR
POR(trip)
again. The
before it
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