ISP1507EBS,518 NXP Semiconductors, ISP1507EBS,518 Datasheet - Page 45

• Manufacturer Part Number: ISP1507EBS,518
• Description: RF Transceiver USB 2.0 ULPI TRNSCVR
• Manufacturer: NXP Semiconductors

Specifications of ISP1507EBS,518

• Number Of Transceivers: 1
• Esd Protection: YeskV
• Power Supply Requirement: Single
• Operating Supply Voltage (typ): 3.3V
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Dual Supply Voltage (typ): Not RequiredV
• Dual Supply Voltage (max): Not RequiredV
• Dual Supply Voltage (min): Not RequiredV
• Mounting: Surface Mount
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Lead Free Status / RoHS Status: Compliant
• Other names: 935285498518 ISP1507EBS-T

NXP Semiconductors
10. Register map
Table 18.
[1]
[2]
[3]
[4]
Table 19.
[1]
[2]
[3]
[4]
ISP1507E_ISP1507F_1
Product data sheet
Field name
VENDOR_ID_LOW
VENDOR_ID_HIGH
PRODUCT_ID_LOW
PRODUCT_ID_HIGH
FUNC_CTRL
INTF_CTRL
OTG_CTRL
USB_INTR_EN_R_E
USB_INTR_EN_F_E
USB_INTR_STAT
USB_INTR_L
DEBUG
SCRATCH
Reserved (do not use)
Access extended register set
Vendor-specific register
PWR_CTRL
Field name
Maps to immediate register set above
Reserved (do not use)
Read (R): A register can be read. Read-only if this is the only mode given.
Write (W): The pattern on the data bus will be written over all bits of a register.
Set (S): The pattern on the data bus is OR-ed with and written to a register.
Clear (C): The pattern on the data bus is a mask. If a bit in the mask is set, then the corresponding register bit will be set to zero
(cleared).
Read (R): A register can be read. Read-only if this is the only mode given.
Write (W): The pattern on the data bus will be written over all bits of a register.
Set (S): The pattern on the data bus is OR-ed with and written to a register.
Clear (C): The pattern on the data bus is a mask. If a bit in the mask is set, then the corresponding register bit will be set to zero
(cleared).
Immediate register set overview
Extended register set overview
Size
(bit)
8
8
8
8
8
8
8
8
8
8
8
8
8
-
8
8
8
Size
(bit)
8
8
R
00h
01h
02h
03h
04h to 06h
07h to 09h
0Ah to 0Ch 0Ah
0Dh to 0Fh 0Dh
10h to 12h
13h
14h
15h
16h to 18h
-
[1]
R
[1]
Rev. 01 — 28 May 2008
W
-
-
-
-
04h
07h
10h
-
-
-
16h
2Fh
W
Address (6 bit)
[2]
Address (6 bit)
[2]
30h to 3Ch
3Dh to 3Fh
19h to 2Eh
40h to FFh
00h to 3Fh
S
-
-
-
-
05h
08h
0Bh
0Eh
11h
-
-
-
17h
-
S
[3]
[3]
ISP1507E; ISP1507F
C
-
-
-
-
06h
09h
0Ch
0Fh
12h
-
-
-
18h
-
C
[4]
[4]
ULPI HS USB OTG transceiver
References
Section 10.1.1 on page 45
Section 10.1.2 on page 45
Section 10.1.3 on page 46
Section 10.1.4 on page 47
Section 10.1.5 on page 49
Section 10.1.6 on page 49
Section 10.1.7 on page 50
Section 10.1.8 on page 50
Section 10.1.9 on page 51
Section 10.1.10 on page 51
Section 10.1.11 on page 52
Section 10.1.12 on page 52
Section 10.1.13 on page 52
Section 10.1.14 on page 52
References
Section 10.2 on page 52
© NXP B.V. 2008. All rights reserved.
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