ISP1507EBS,518 NXP Semiconductors, ISP1507EBS,518 Datasheet - Page 76

• Manufacturer Part Number: ISP1507EBS,518
• Description: RF Transceiver USB 2.0 ULPI TRNSCVR
• Manufacturer: NXP Semiconductors

Specifications of ISP1507EBS,518

• Number Of Transceivers: 1
• Esd Protection: YeskV
• Power Supply Requirement: Single
• Operating Supply Voltage (typ): 3.3V
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Dual Supply Voltage (typ): Not RequiredV
• Dual Supply Voltage (max): Not RequiredV
• Dual Supply Voltage (min): Not RequiredV
• Mounting: Surface Mount
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Lead Free Status / RoHS Status: Compliant
• Other names: 935285498518 ISP1507EBS-T

NXP Semiconductors
24. Tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10. RXCMD byte format . . . . . . . . . . . . . . . . . . . . .25
Table 11. LINESTATE[1:0] encoding for upstream
Table 12. LINESTATE[1:0] encoding for downstream
Table 13. Encoded V
Table 14. V
Table 15. Encoded USB event signals . . . . . . . . . . . . . .28
Table 16. PHY pipeline delays . . . . . . . . . . . . . . . . . . . . .32
Table 17. Link decision times . . . . . . . . . . . . . . . . . . . . .33
Table 18. Immediate register set overview . . . . . . . . . . .44
Table 19. Extended register set overview . . . . . . . . . . . .44
Table 20. VENDOR_ID_LOW - Vendor ID Low
Table 21. VENDOR_ID_HIGH - Vendor ID High
Table 22. PRODUCT_ID_LOW - Product ID Low
Table 23. PRODUCT_ID_HIGH - Product ID High
Table 24. FUNC_CTRL - Function Control register
Table 25. FUNC_CTRL - Function Control register
Table 26. INTF_CTRL - Interface Control register
Table 27. INTF_CTRL - Interface Control register
Table 28. OTG_CTRL - OTG Control register
Table 29. OTG_CTRL - OTG Control register
Table 30. USB_INTR_EN_R_E - USB Interrupt Enable
Table 31. USB_INTR_EN_R_E - USB Interrupt Enable
Table 32. USB_INTR_EN_F_E - USB Interrupt Enable
ISP1507E_ISP1507F_1
Product data sheet
Ordering information . . . . . . . . . . . . . . . . . . . . .3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .5
Recommended charge pump capacitor value .12
ULPI signal description . . . . . . . . . . . . . . . . . .15
Signal mapping during low-power mode . . . . .16
Signal mapping for 3-pin serial mode . . . . . . .17
Operating states and their corresponding
resistor settings . . . . . . . . . . . . . . . . . . . . . . . .18
OTG_CTRL register power control bits . . . . . .23
TXCMD byte format . . . . . . . . . . . . . . . . . . . . .24
facing ports: peripheral . . . . . . . . . . . . . . . . . .26
facing ports: host . . . . . . . . . . . . . . . . . . . . . . .26
typical applications . . . . . . . . . . . . . . . . . . . . . .27
register (address R = 00h) bit description . . . .45
register (address R = 01h) bit description . . . .45
register (address R = 02h) bit description . . . .45
register (address R = 03h) bit description . . . .45
(address R = 04h to 06h, W = 04h, S = 05h,
C = 06h) bit allocation . . . . . . . . . . . . . . . . . . .45
(address R = 04h to 06h, W = 04h, S = 05h,
C = 06h) bit description . . . . . . . . . . . . . . . . . .46
(address R = 07h to 09h, W = 07h, S = 08h,
C = 09h) bit allocation . . . . . . . . . . . . . . . . . . .47
(address R = 07h to 09h, W = 07h, S = 08h,
C = 09h) bit description . . . . . . . . . . . . . . . . . .47
(address R = 0Ah to 0Ch, W = 0Ah, S = 0Bh,
C = 0Ch) bit allocation . . . . . . . . . . . . . . . . . . .48
(address R = 0Ah to 0Ch, W = 0Ah, S = 0Bh,
C = 0Ch) bit description . . . . . . . . . . . . . . . . . .48
Rising Edge register (address R = 0Dh to 0Fh,
W = 0Dh, S = 0Eh, C = 0Fh) bit allocation . . . .49
Rising Edge register (address R = 0Dh to 0Fh,
W = 0Dh, S = 0Eh, C = 0Fh) bit description . .49
BUS
indicators in RXCMD required for
BUS
voltage state . . . . . . . . . . . . . .26
Rev. 01 — 28 May 2008
Table 33. USB_INTR_EN_F_E - USB Interrupt Enable
Table 34. USB_INTR_STAT - USB Interrupt Status
Table 35. USB_INTR_STAT - USB Interrupt Status
Table 36. USB_INTR_L - USB Interrupt Latch
Table 37. USB_INTR_L - USB Interrupt Latch
Table 38. DEBUG - Debug register (address R = 15h)
Table 39. DEBUG - Debug register (address R = 15h)
Table 40. SCRATCH - Scratch register
Table 41. PWR_CTRL - Power Control register
Table 42. PWR_CTRL - Power Control register
Table 43. Limiting values . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 44. Recommended operating conditions . . . . . . . . 54
Table 45. Static characteristics: supply pins . . . . . . . . . . 55
Table 46. Static characteristics: digital pins
Table 47. Static characteristics: digital pin FAULT . . . . . 56
Table 48. Static characteristics: analog I/O pins
Table 49. Static characteristics: charge pump . . . . . . . . 58
Table 50. Static characteristics: V
Table 51. Static characteristics: V
Table 52. Static characteristics: ID detection circuit . . . . 58
Table 53. Static characteristics: resistor reference . . . . . 59
Table 54. Dynamic characteristics: reset and clock . . . . 60
Table 55. Dynamic characteristics: digital I/O pins . . . . . 61
Table 56. Dynamic characteristics: analog I/O pins
Table 57. Recommended bill of materials . . . . . . . . . . . . 64
Table 58. SnPb eutectic process (from J-STD-020C) . . . 71
Table 59. Lead-free process (from J-STD-020C) . . . . . . 71
Table 60. Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Table 61. Revision history . . . . . . . . . . . . . . . . . . . . . . . . 73
Falling Edge register (address R = 10h to 12h,
W = 10h, S = 11h, C = 12h) bit allocation . . . . 49
Falling Edge register (address R = 10h to 12h,
W = 10h, S = 11h, C = 12h) bit description . . . 50
register (address R = 13h) bit allocation . . . . . 50
register (address R = 13h) bit description . . . . 50
register (address R = 14h) bit allocation . . . . . 51
register (address R = 14h) bit description . . . . 51
bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . 51
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 51
(address R = 16h to 18h, W = 16h, S = 17h,
C = 18h) bit description . . . . . . . . . . . . . . . . . . 51
(address R = 3Dh to 3Fh, W = 3Dh, S = 3Eh,
C = 3Fh) bit allocation . . . . . . . . . . . . . . . . . . . 52
(address R = 3Dh to 3Fh, W = 3Dh, S = 3Eh,
C = 3Fh) bit description . . . . . . . . . . . . . . . . . . 52
(CLOCK, DIR, STP, NXT, DATA[3:0],
RESET_N/PSW_N) . . . . . . . . . . . . . . . . . . . . . 55
(DP, DM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
(DP and DM) . . . . . . . . . . . . . . . . . . . . . . . . . . 61
ISP1507E; ISP1507F
ULPI HS USB OTG transceiver
BUS
BUS
comparators . . . . 58
resistors . . . . . . . . 58
© NXP B.V. 2008. All rights reserved.
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