MT45W512KW16PGA-70 WT Micron Technology Inc, MT45W512KW16PGA-70 WT Datasheet - Page 13

• Manufacturer Part Number: MT45W512KW16PGA-70 WT
• Manufacturer: Micron Technology Inc

Specifications of MT45W512KW16PGA-70 WT

• Operating Temperature (max): 85C
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Compliant

Figure 12:
Partial Array Refresh (CR[2:0]) Default = Full Array Refresh
Table 3:
Sleep Mode (CR[4]) Default = PAR Enabled, DPD Disabled
PDF: 09005aef8220472e/Source: 09005aef8220461e
8mb_asyncpage_ps1_0_p23z.fm - Rev. A 7/06 EN
RCR[2]
0
0
0
0
1
1
1
1
RCR[1]
8Mb Address Patterns for PAR (RCR[4] = 1)
Configuration Register Bit Mapping
0
0
1
1
0
0
1
1
RCR[0]
CR[6] CR[5]
CR[7]
1
1
0
0
0
1
0
1
0
1
0
1
0
1
The PAR bits restrict refresh operation to a portion of the total memory array. This
feature allows the system to reduce current by only refreshing that part of the memory
array required by the host system. The refresh options are: full array, one-half array, one-
quarter array, one-eighth array, or none of the array. The mapping of these partitions can
start at either the beginning or the end of the address map (see Table 3).
The sleep mode bit determines which low-power mode is to be entered when ZZ# is
driven LOW. If CR[4] = 1, PAR operation is enabled. If CR[4] = 0, DPD operation is
enabled. PAR can also be enabled directly by writing to the CR using the software access
sequence. Note that this then disables ZZ# initiation of PAR. DPD cannot be enabled or
disabled using the software access sequence; this should only be done using ZZ# to
access the CR.
All must be set to “0”
1
0
1
0
Page Mode Enable/Disable
Page Mode Disabled (default)
Page Mode Enabled
RESERVED
Internal sensor (default)
+45˚C
+15˚C
Maximum Case Temp.
+85˚C
A[18:8]
18–8
One-quarter of die
One-quarter of die
One-eighth of die
One-eighth of die
Active Section
One-half of die
One-half of die
None of die
Full die
PAGE
7
A7
13
6
TCR
A6
5
A5
000000h–07FFFFh
000000h–03FFFFh
000000h–01FFFFh
000000h–00FFFFh
40000h–07FFFFh
60000h–07FFFFh
70000h–07FFFFh
Address Space
Configuration Register (CR) Operation
SLEEP
CR[4]
Micron Technology, Inc., reserves the right to change products or specifications without notice.
0
1
4
A4
Must be set to “0”
8Mb: 512K x 16 Async/Page PSRAM
0
RESERVED
Sleep Mode
DPD Enabled
PAR Enabled (default)
3
A3
CR[2]
2
A2
0
0
0
0
1
1
1
1
0 Meg x 16
512K x 16
256K x 16
128K x 16
256K x 16
128K x 16
CR[1] CR[0]
64K x 16
64K x 16
0
0
1
1
0
0
1
1
Size
©2006 Micron Technology, Inc. All rights reserved.
PAR
1
A1
0
1
0
1
0
1
0
1
PAR Coverage
Full array (default)
Bottom 1/2 array
Bottom 1/4 array
Bottom 1/8 array
None of array
Top 1/2 array
Top 1/4 array
Top 1/8 array
0
A0
Density
8Mb
4Mb
2Mb
1Mb
0Mb
4Mb
2Mb
1Mb
Address Bus
Advance