MT45W512KW16PGA-70 WT Micron Technology Inc, MT45W512KW16PGA-70 WT Datasheet - Page 4
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MT45W512KW16PGA-70 WT
Manufacturer Part Number
MT45W512KW16PGA-70 WT
Description
Manufacturer
Micron Technology Inc
Datasheet
1.MT45W512KW16PGA-70_WT.pdf
(24 pages)
Specifications of MT45W512KW16PGA-70 WT
Operating Temperature (max)
85C
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / RoHS Status
Compliant
Bus Operations
Table 2:
PDF: 09005aef8220472e/Source: 09005aef8220461e
8mb_asyncpage_ps1_0_p23z.fm - Rev. A 7/06 EN
Mode
Standby
Read
Write
No operation
PAR
DPD
Load
configuration
register
Bus Operations
Partial-array refresh
Deep power-down
Notes:
Standby
Power
Active
Active
Active
Idle
2. V
3. When LB# and UB# are in select mode (LOW), DQ[15:0] are affected. When LB# alone is in
4. The device will consume active power in this mode whenever addresses are changed.
5. When WE# is active, the OE# input is internally disabled and has no effect on the I/Os.
6. DPD is enabled when configuration register bit CR[4] is “0”; otherwise, PAR is enabled.
1. When the device is in standby mode, control inputs (WE#, OE#), address inputs, and data
inputs/outputs are internally isolated from any external influence.
standby current.
select mode, only DQ[7:0] are affected. When UB# alone is in the select mode, only DQ[15:8]
are affected.
IN
= V
CC
Q or 0V; all device balls must be static (unswitched) in order to achieve minimum
CE#
H
H
H
L
L
L
L
WE#
X
H
X
X
X
L
L
4
OE#
X
X
X
X
X
X
L
LB#/UB#
Micron Technology, Inc., reserves the right to change products or specifications without notice.
X
X
X
X
X
L
L
8Mb: 512K x 16 Async/Page PSRAM
ZZ#
H
H
H
H
L
L
L
©2006 Micron Technology, Inc. All rights reserved.
DQ[15:0]
Data-out
Data-in
High-Z
High-Z
High-Z
High-Z
X
Bus Operations
1
Notes
Advance
3, 5, 4
1, 2
3, 4
4, 2
6
6