MT45W512KW16PGA-70 WT Micron Technology Inc, MT45W512KW16PGA-70 WT Datasheet - Page 8

• Manufacturer Part Number: MT45W512KW16PGA-70 WT
• Manufacturer: Micron Technology Inc

Specifications of MT45W512KW16PGA-70 WT

• Operating Temperature (max): 85C
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Compliant

Page Mode READ Operation
Figure 7:
LB#/UB# Operation
PDF: 09005aef8220472e/Source: 09005aef8220461e
8mb_asyncpage_ps1_0_p23z.fm - Rev. A 7/06 EN
Page READ Operation
Page mode is a performance-enhancing extension to the legacy asynchronous READ
operation. In page-mode-capable products, an initial asynchronous read access is
performed. Adjacent addresses can then be quickly read by simply changing the low-
order address. Addresses A[3:0] are used to determine the members of the 16-address
PSRAM page. Any change in addresses A[4] or higher will initiate a new
Figure 7 shows the timing diagram for a page mode access.
Page mode takes advantage of the fact that adjacent addresses can be read in a shorter
period of time than random addresses. WRITE operations do not include comparable
page mode functionality.
The CE# LOW time is limited by refresh considerations. CE# must not stay LOW longer
than
ADDRESS
The lower byte (LB#) enable and upper byte (UB#) enable signals allow for byte-wide
data transfers. During READ operations, enabled bytes are driven onto the DQs. The
DQs associated with a disabled byte are put into a High-Z state during a READ opera-
tion. During WRITE operations, any disabled bytes will not be transferred to the memory
array and the internal value will remain unchanged. During a WRITE cycle, the data to
be written is latched on the rising edge of CE#, WE#, LB#, or UB#, whichever occurs first.
When both the LB# and UB# are disabled (HIGH) during an operation, the device will
disable the data bus from receiving or transmitting data. Although the device will appear
to be deselected, it remains in an active mode as long as CE# is LOW.
LB#/UB#
DATA
WE#
OE#
CE#
CE#
t
CEM.
ADDRESS[0]
t AA
D[0]
8
ADDRESS
t APA
[1]
< t CEM
D[1]
ADDRESS
t APA
[2]
Micron Technology, Inc., reserves the right to change products or specifications without notice.
D[2]
ADDRESS
t APA
8Mb: 512K x 16 Async/Page PSRAM
[3]
D[3]
DON'T CARE
Bus Operating Modes
©2006 Micron Technology, Inc. All rights reserved.
t
AA access.
Advance