MT45W512KW16PGA-70 WT Micron Technology Inc, MT45W512KW16PGA-70 WT Datasheet - Page 6

• Manufacturer Part Number: MT45W512KW16PGA-70 WT
• Manufacturer: Micron Technology Inc

Specifications of MT45W512KW16PGA-70 WT

• Operating Temperature (max): 85C
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Compliant

Functional Description
Power-Up Initialization
Figure 4:
Bus Operating Modes
Asynchronous Mode
PDF: 09005aef8220472e/Source: 09005aef8220461e
8mb_asyncpage_ps1_0_p23z.fm - Rev. A 7/06 EN
Power-Up Initialization Timing
In general, the MT45W512KW16P device is a high-density alternative to SRAM and
PSRAM products, popular in low-power, portable applications. The MT45W512KW16P
contains an 8,388,608-bit DRAM core organized as 524,288 addresses by 16 bits. These
devices include the industry-standard, asynchronous memory interface found on other
low-power SRAM or PSRAM offerings. Page mode accesses are also included as a band-
width-enhancing extension to the asynchronous read protocol.
Micron PSRAM products include an on-chip voltage sensor that is used to launch the
power-up initialization process. Initialization will load the CR with its default setting.
V
1.7V, the device will require 150µs to complete its self-initialization process (see
Figure 4). During the initialization period, CE# should remain HIGH. When initialization
is complete, the device is ready for normal operation.
Vcc, VccQ = 1.7V
The MT45W512KW16P PSRAM product incorporates the industry-standard, asynchro-
nous interface found on other low-power SRAM or PSRAM offerings. This bus interface
supports asynchronous READ and WRITE operations as well as the bandwidth-
enhancing page mode READ operation. The specific interface that is supported is
defined by the value loaded into the CR.
Micron PSRAM products power up in the asynchronous operating mode. This mode
uses the industry-standard SRAM control interface (CE#, OE#, WE#, LB#/UB#). READ
operations (Figure 5 on page 7) are initiated by bringing CE#, OE#, and LB#/UB# LOW
while keeping WE# HIGH. Valid data will be driven out of the I/Os after the specified
access time has elapsed. WRITE operations (Figure 6 on page 7) occur when CE#, WE#,
and LB#/UB# are driven LOW. During WRITE operations, the level of OE# is a “Don't
Care”; WE# will override OE#. The data to be written will be latched on the rising edge of
CE#, WE#, or LB#/UB# (whichever occurs first). WE# LOW time must be limited to
CC
and V
CC
Q must be applied simultaneously, and when they reach a stable level above
t PU
6
Micron Technology, Inc., reserves the right to change products or specifications without notice.
8Mb: 512K x 16 Async/Page PSRAM
normal operation
Device ready for
Vcc (MIN)
Functional Description
©2006 Micron Technology, Inc. All rights reserved.
Advance
t
CEM.