MT45W512KW16PGA-70 WT Micron Technology Inc, MT45W512KW16PGA-70 WT Datasheet - Page 2

• Manufacturer Part Number: MT45W512KW16PGA-70 WT
• Manufacturer: Micron Technology Inc

Specifications of MT45W512KW16PGA-70 WT

• Operating Temperature (max): 85C
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Compliant

General Description
Functional Block Diagram
Figure 2:
PDF: 09005aef8220472e/Source: 09005aef8220461e
8mb_asyncpage_ps1_0_p23z.fm - Rev. A 7/06 EN
Functional Block Diagram 512K x 16
Notes:
WE#
OE#
UB#
CE#
LB#
ZZ#
Micron
low-power, portable applications. The MT45W512KW16P is an 8Mb DRAM core device
organized as 512K x 16 bits. These devices include the industry-standard, asynchronous
memory interface found on other low-power SRAM or PSRAM offerings.
A user-accessible configuration register (CR) defines how the PSRAM device performs
on-chip refresh and whether page mode read accesses are permitted. This register is
automatically loaded with a default setting during power up and can be updated at any
time during normal operation.
To ensure seamless operation on an asynchronous memory bus, PSRAM products incor-
porate a transparent self refresh mechanism. The hidden refresh requires no additional
support from the system memory controller and has no significant impact on device
read/write performance.
Special attention has been focused on current consumption during self refresh. These
PSRAM products include three system-accessible mechanisms to minimize refresh
current. Temperature-compensated refresh (TCR) uses an on-chip sensor to adjust the
refresh rate to match the device temperature. The refresh rate decreases at lower
temperatures to minimize current consumption during standby. TCR can also be set by
the system for maximum device temperatures of +85°C, +45°C, and +15°C. Setting sleep
enable (ZZ#) to LOW enables one of two low-power modes: partial-array refresh (PAR) or
deep power-down (DPD). PAR limits refresh to only that part of the DRAM array that
contains essential data. DPD halts refresh operation altogether and is used when no vital
information is stored in the device. These three refresh mechanisms are accessed
through the CR.
1. Functional block diagrams illustrate simplified device operation. See truth table, ball
A[18:0]
descriptions, and timing diagrams for detailed information.
®
Control
PSRAM products are high-speed, CMOS PSRAM memory devices developed for
Logic
Address Decode
Configuration
Register (CR)
2
Logic
Micron Technology, Inc., reserves the right to change products or specifications without notice.
8Mb: 512K x 16 Async/Page PSRAM
512K x 16
Memory
DRAM
Array
General Description
©2006 Micron Technology, Inc. All rights reserved.
Output
Buffers
Input/
MUX
and
DQ[15:8]
DQ[7:0]
Advance