FW82801ER S L742 Intel, FW82801ER S L742 Datasheet - Page 305
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FW82801ER S L742
Manufacturer Part Number
FW82801ER S L742
Description
Manufacturer
Intel
Datasheet
1.FW82801ER_S_L742.pdf
(671 pages)
Specifications of FW82801ER S L742
Lead Free Status / RoHS Status
Not Compliant
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8.1.5
8.1.6
8.1.7
8.1.8
Intel
®
82801EB ICH5 / 82801ER ICH5R Datasheet
BCC—Base-Class Code Register
RID—Revision Identification Register
(HUB-PCI—D30:F0)
Offset Address:
Default Value:
SCC—Sub-Class Code Register
(HUB-PCI—D30:F0)
Offset Address:
Default Value:
(HUB-PCI—D30:F0)
Offset Address:
Default Value:
PMLT—Primary Master Latency Timer Register
(HUB-PCI—D30:F0)
Offset Address:
Default Value:
This register does not apply to hub interface.
Bit
7:0
Bit
7:0
Bit
7:0
Bit
7:3
2:0
Revision ID — RO. 8-bit value that indicates the revision number for the Intel
PCI bridge.
NOTE: Refer to the latest Intel
Sub Class Code (SCC) — RO. This 8-bit value indicates the category of bridge for the Intel
hub interface to PCI bridge.
04h = PCI-to-PCI bridge.
Base Class Code (BCC) — RO. This 8-bit value indicates the type of device for the Intel
interface to PCI bridge.
06h = Bridge device.
Master Latency Timer Count (MLTC) — RO. Not implemented.
Reserved
Identification register.
08h
See bit Description
0Ah
04h
0Bh
06h
0Dh
00h
®
ICH5 / ICH5R Specification Update for the value of the Revision
Hub Interface to PCI Bridge Registers (D30:F0)
Description
Description
Description
Description
Attribute:
Size:
Attribute:
Size:
Attribute:
Size:
Attribute:
Size:
RO
8 bits
RO
8 bits
RO
8 bits
RO
8 bits
®
ICH5 hub interface to
®
ICH5 hub
®
ICH5
305
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