FW82801ER S L742 Intel, FW82801ER S L742 Datasheet - Page 44
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FW82801ER S L742
Manufacturer Part Number
FW82801ER S L742
Description
Manufacturer
Intel
Datasheet
1.FW82801ER_S_L742.pdf
(671 pages)
Specifications of FW82801ER S L742
Lead Free Status / RoHS Status
Not Compliant
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Introduction
44
Compatibility Modules (DMA Controller, Timer/Counters, Interrupt
Controller)
The DMA controller incorporates the logic of two 82C37 DMA controllers, with seven
independently programmable channels. Channels 0–3 are hardwired to 8-bit, count-by-byte
transfers, and channels 5–7 are hardwired to 16-bit, count-by-word transfers. Any two of the seven
DMA channels can be programmed to support fast Type-F transfers.
The ICH5 supports two types of DMA (LPC and PC/PCI). DMA via LPC is similar to ISA DMA.
LPC DMA and PC/PCI DMA use the ICH5’s DMA controller. The PC/PCI protocol allows
PCI-based peripherals to initiate DMA cycles by encoding requests and grants via two PC/PCI
REQ#/GNT# pairs.
LPC DMA is handled through the use of the LDRQ# lines from peripherals and special encoding
on LAD[3:0] from the host. Single, Demand, Verify, and Increment modes are supported on the
LPC interface. Channels 0–3 are 8 bit channels. Channels 5–7 are 16 bit channels. Channel 4 is
reserved as a generic bus master request.
The timer/counter block contains three counters that are equivalent in function to those found in
one 82C54 programmable interval timer. These three counters are combined to provide the system
timer function, and speaker tone. The 14.31818 MHz oscillator input provides the clock source for
these three counters.
The ICH5 provides an ISA-compatible Programmable Interrupt Controller (PIC) that incorporates
the functionality of two 82C59 interrupt controllers. The two interrupt controllers are cascaded so
that 14 external and two internal interrupts are possible. In addition, the ICH5 supports a serial
interrupt scheme.
All of the registers in these modules can be read and restored. This is required to save and restore
system state after power has been removed and restored to the platform.
Advanced Programmable Interrupt Controller (APIC)
In addition to the standard ISA-compatible PIC described in the previous section, the ICH5
incorporates the Advanced Programmable Interrupt Controller (APIC).
Universal Serial Bus (USB) Controller
The ICH5 contains an Enhanced Host Controller Interface Specification for Universal Serial Bus,
Revision 1.0 -compliant host controller that supports USB high-speed signaling. High-speed USB
2.0 allows data transfers up to 480 Mb/s which is 40 times faster than full-speed USB. The ICH5
also contains four Universal Host Controller Interface (UHCI) controllers that support USB full-
speed and low-speed signaling.
The ICH5 supports eight USB 2.0 ports. All eight ports are high-speed, full-speed, and low-speed
capable. ICH5’s port-routing logic determines whether a USB port is controlled by one of the
UHCI controllers or by the EHCI controller. See
Intel
Section 5.19
®
82801EB ICH5 / 82801ER ICH5R Datasheet
and
Section 5.20
for details.
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