FW82801ER S L742 Intel, FW82801ER S L742 Datasheet - Page 324
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FW82801ER S L742
Manufacturer Part Number
FW82801ER S L742
Description
Manufacturer
Intel
Datasheet
1.FW82801ER_S_L742.pdf
(671 pages)
Specifications of FW82801ER S L742
Lead Free Status / RoHS Status
Not Compliant
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LPC Interface Bridge Registers (D31:F0)
9.1.12
9.1.13
324
BIOS_CNTL—BIOS Control Register
(LPC I/F—D31:F0)
Offset Address:
Default Value:
Lockable:
TCO_CNTL — TCO Control Register
(LPC I/F — D31:F0)
Offset Address:
Default Value:
Lockable:
15:2
Bit
1
0
Bit
7:4
2:0
3
Reserved
BIOS Lock Enable (BLE) — R/W.
0 = Setting the BIOSWE will not cause Sums. Once set, this bit can only be cleared by a PCIRST#.
1 = Enables setting the BIOSWE bit to cause Sums.
BIOS Write Enable (BIOSWE) — R/W.
0 = Only read cycles result in flash BIOS I/F cycles.
1 = Access to the BIOS space is enabled for both read and write cycles. When this bit is written
Reserved
TCO Interrupt Enable (TCO_INT_EN) — R/W. This bit enables/disables the TCO interrupt.
0 = Disables TCO interrupt.
1 = Enables TCO Interrupt, as selected by the TCO_INT_SEL field.
TCO Interrupt Select (TCO_INT_SEL) — R/W. This field specifies on which IRQ the TCO will
internally appear. If not using the APIC, the TCO interrupt must be routed to IRQ9–11, and that
interrupt is not sharable with the SERIRQ stream, but is shareable with other PCI interrupts. If
using the APIC, the TCO interrupt can also be mapped to IRQ20–23, and can be shared with
other interrupt. Note that if the TCOSCI_EN bit is set (bit 6 of the GPEO_EN register), then the
TCO interrupt will be sent to the same interrupt as the SCI, and the TCO_INT_SEL bits will have
no meaning. When the TCO interrupt is mapped to APIC interrupts 9, 10 or 11, the signal is in fact
active high. When the TCO interrupt is mapped to IRQ 20, 21, 22, or 23, the signal is active low
and can be shared with PCI interrupts that may be mapped to those same signals (IRQs).
Bits
000
001
010
011
100
101
110
111
from a 0 to a 1 and BIOS Lock Enable (BLE) is also set, an SMI# is generated. This ensures
that only SMI code can update BIOS.
4E
0000h
No
54h
00h
No
SCI Map
IRQ9
IRQ10
IRQ11
Reserved
IRQ20 (Only available if APIC enabled)
IRQ21 (Only available if APIC enabled)
IRQ22 (Only available if APIC enabled)
IRQ23 (Only available if APIC enabled)
–
4Fh
Intel
Description
Description
Attribute:
Size:
Power Well:
Attribute:
Size:
Power Well:
®
82801EB ICH5 / 82801ER ICH5R Datasheet
R/W
16 bit
Core
R/W
8 bit
Core
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