ISP1181BDGG,112 STEricsson, ISP1181BDGG,112 Datasheet
ISP1181BDGG,112
Specifications of ISP1181BDGG,112
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ISP1181BDGG,112 Summary of contents
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... If you have any questions related to the document, please contact our nearest sales office or wired.support@stericsson.com. Thank you for your cooperation and understanding. ...
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ISP1181B Full-speed USB peripheral controller Rev. 03 — 23 January 2009 1. General description The ISP1181B is a Universal Serial Bus (USB) peripheral controller that complies with Universal Serial Bus Specification Rev. 2.0, supporting data transfer at full-speed (12 Mbit/s). ...
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Clock output with programmable frequency ( MHz) Complies with the ACPI, OnNow and USB power management requirements Internal power-on and low-voltage reset circuit, with possibility of a software reset Operation over the extended USB bus voltage range (4.0 ...
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USB V BUS sense input to LED 3.3 V HUB GoodLink 1.5 k SoftConnect ANALOG Tx/Rx 44 RESET POWER-ON internal ...
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Pinning information 6.1 Pinning Fig 2. Pin configuration TSSOP48. ISP1181B_3 Product data sheet Full-speed USB peripheral controller REGGND reg(3. BUS ...
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Fig 3. Pin configuration HVQFN48. 6.2 Pin description Table 2. [1] Symbol V CC REGGND V reg(3. BUS GL WAKEUP SUSPEND ISP1181B_3 Product data sheet BUS_CONF0 12 TEST3 11 INT 10 TEST2 9 8 TEST1 7 DACK ...
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Table 2. [1] Symbol EOT DREQ DACK TEST1 TEST2 INT TEST3 BUS_CONF0 BUS_CONF1 DATA15 DATA14 DATA13 DATA12 DATA11 DATA10 GND V ref DATA9 DATA8 DATA7 DATA6 ISP1181B_3 Product data sheet Pin description …continued Pin Type TSSOP48 HVQFN48 ...
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Table 2. [1] Symbol DATA5 DATA4 DATA3 DATA2 DATA1 GND V CC(3.3) AD0 ALE CS RESET CLKOUT ISP1181B_3 Product data sheet Pin description …continued Pin Type TSSOP48 HVQFN48 I/O ...
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Table 2. [1] Symbol GND XTAL2 XTAL1 [1] Symbol names with an overscore (for example, NAME) represent active LOW signals. ISP1181B_3 Product data sheet Pin description …continued Pin Type TSSOP48 HVQFN48 ...
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Functional description The ISP1181B is a full-speed USB peripheral controller with configurable endpoints. It has a fast general-purpose parallel interface for communication with many types of microcontrollers or microprocessors. It supports different bus configurations (see Table ...
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V sensing prevents the peripheral from wake-up when V BUS V sensing, any activity or noise on (D+, D-) might wake up the peripheral. With V BUS sensing, (D+, D-) is decoupled when the (D+, D-) lines, ...
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Modes of operation The ISP1181B has four bus configuration modes, selected via pins BUS_CONF1 and BUS_CONF0: Mode 0 Mode 1 Mode 2 Mode 3 The bus configurations for each of these modes are given in circuits for each mode ...
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Table 4. Endpoint access and programmability [1] Endpoint FIFO size (bytes) identifier 0 64 (fixed (fixed) 1 programmable 2 programmable 3 programmable 4 programmable 5 programmable 6 programmable 7 programmable 8 programmable 9 programmable 10 programmable 11 programmable ...
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Table 5. FFOSZ[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Each programmable FIFO can be configured independently via its ECR, but the total physical size of all enabled endpoints (IN plus ...
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Endpoint initialization In response to the standard USB request, Set Interface, the firmware must program all 16 ECRs of the ISP1181B in sequence (see or not. The hardware will then automatically allocate FIFO storage space. If all endpoints have ...
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DMA transfer Direct Memory Access (DMA method to transfer data from one location to another in a computer system, without intervention of the central processor (CPU). Many different implementations of DMA exist. The ISP1181B supports two methods: ...
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Table 7. Endpoint identifier 10.2 8237 compatible mode The 8237 compatible DMA mode is selected by clearing bit DAKOLY in the Hardware Configuration Register (see Table 8. Table 8. Symbol DREQ DACK EOT RD WR The DMA ...
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The following example shows the steps which occur in a typical DMA transfer: 1. ISP1181B receives a data packet in one of its endpoint FIFOs; the packet must be transferred to memory address 1234H. 2. ISP1181B asserts the DREQ signal ...
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In DACK-only mode the ISP1181B uses the DACK signal as data strobe. Input signals RD and WR are ignored. This mode is used in CPU systems that have a single address space for memory and I/O access. Such systems have ...
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Short packet Normally, the transfer byte count must be set via a control endpoint before any DMA transfer takes place. When a short packet has been enabled as EOT indicator (SHORTP = 1), the transfer size is determined by ...
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Suspend and resume 11.1 Suspend conditions The ISP1181B detects a USB suspend status when a constant idle state is present on the USB bus for more than 3 ms. The bus-powered devices that are suspended must not consume more ...
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A USB bus INT_N GOSUSP WAKEUP SUSPEND Fig 6. Suspend and resume timing. In Figure 6: • A: indicates the point at which the USB bus enters the idle state. • B: indicates resume condition, which can ...
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Fig 7. SUSPEND and WAKEUP signals in a powered-off modem application. 11.2 Resume conditions A wake-up from the suspend state is initiated either by the USB host or by the application: • USB host: drives a K-state on the USB ...
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Table 12. Register Mode Hardware Configuration Unlock 12. Commands and registers The functions and registers of ISP1181B are accessed via commands, which consist of a command code followed by optional data bytes (read or write action). An overview of the ...
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Table 13. Command and register summary Name Read Endpoint n Configuration ( 14) Write/Read Device Address Write/Read Mode Register Write/Read Hardware Configuration Hardware Configuration Register Write/Read Interrupt Enable Register Write/Read DMA Configuration Write/Read DMA Counter Reset Device ...
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Table 13. Command and register summary Name [7] Check Control IN Status Check Endpoint n Status [ 14) Acknowledge Setup General commands Read Control OUT Error Code Read Control IN Error Code Read Endpoint n Error ...
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Code (Hex — write (control OUT, control IN, endpoint 1 to 14) Code (Hex — read (control OUT, control IN, endpoint 1 to 14) Transaction — write/read 1 byte Table 14. Endpoint Configuration Register: ...
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Write/Read Mode Register This command is used to access the ISP1181B Mode Register, which consists of 1 byte (bit allocation: see The Mode Register controls the DMA bus width, resume and suspend modes, interrupt activity and SoftConnect operation. It ...
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Transaction — write/read 2 bytes Table 20. Hardware Configuration Register: bit allocation Bit 15 14 Symbol reserved EXTPUL Reset 0 0 Access R/W R/W Bit 7 6 Symbol DAKOLY DRQPOL Reset 0 1 Access R/W R/W Table 21. Bit 15 ...
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Table 21. Bit 12.1.5 Write/Read Interrupt Enable Register This command is used to individually enable/disable interrupts from all endpoints, as well as interrupts caused by events on the USB bus (SOF, SOF lost, EOT, suspend, resume, reset). ...
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Table 23. Bit 12.1.6 Write/Read DMA Configuration This command defines the DMA configuration of ISP1181B and enables/disables DMA transfers. The command accesses the DMA Configuration Register, which consists of 2 bytes. The ...
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Table 25. Bit 12.1.7 Write/Read DMA Counter This command accesses the DMA Counter Register, which consists of 2 bytes. The bit allocation is given in transfer. Reading the register returns the number of remaining bytes ...
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Data flow commands Data flow commands are used to manage the data transmission between the USB endpoints and the system microcontroller. Much of the data flow is initiated via an interrupt to the microcontroller. The data flow commands are ...
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Table 29 … Table 30 … Remark: There is no protection against writing or reading past a buffer’s boundary, against writing into an OUT buffer or reading ...
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Table 32. Bit 12.2.3 Stall Endpoint/Unstall Endpoint These commands are used to stall or unstall an endpoint. The commands modify the content of the Endpoint Status Register (see A stalled control endpoint ...
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Clear Endpoint Buffer This command unlocks and clears the buffer of the selected OUT endpoint, allowing the reception of new packets. Reception of a complete packet causes the Buffer Full flag of an OUT endpoint to be set. Any ...
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Acknowledge Setup This command acknowledges to the host that a SETUP packet was received. The arrival of a SETUP packet disables the Validate Buffer and Clear Buffer commands for the control IN and OUT endpoints. The microcontroller needs to ...
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Table 37. Error code (Binary) 0111 1000 1001 1010 1011 1100 1101 1110 1111 12.3.2 Unlock Device This command unlocks the ISP1181B from write-protection mode after a ‘resume’. In ‘suspend’ state all registers and FIFOs are write-protected to prevent data ...
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Transaction — write/read 2 bytes Table 40. Scratch Information Register: bit allocation Bit 15 14 Symbol reserved Reset 0 0 Access R/W R/W Bit 7 6 Symbol Reset 0 0 Access R/W R/W Table 41. Bit ...
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Table 44 Table 45 12.3.5 Read Chip ID This command reads the chip identification code and hardware version number. The firmware must check this information to determine the supported functions and features. This ...
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Table 48. Interrupt Register: bit allocation Bit 31 30 Symbol Reset 0 0 Access R R Bit 23 22 Symbol EP14 EP13 Reset 0 0 Access R R Bit 15 14 Symbol EP6 EP5 Reset 0 0 Access R R ...
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The active level and signalling mode of the INT output is controlled by the INTPOL and INTLVL bits of the Hardware Configuration Register (see reset are active LOW and level mode. When pulse mode is selected, a pulse of 166 ...
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Power supply The ISP1181B is powered from a single supply voltage, ranging from 4 5 integrated voltage regulator provides a 3.3 V supply voltage for the internal logic and the USB transceiver. This voltage is ...
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CLKRUN SUSPEND . . . CLKDIV [ 3 NOLAZY Fig 12. Oscillator and LazyClock logic. When ISP1181B enters ‘suspend’ state (by setting and clearing bit GOSUSP in the Mode Register), outputs SUSPEND and ...
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Power-on reset The ISP1181B has an internal power-on reset (POR) circuit. Input pin RESET can be directly connected to V power-on and normally requires stabilize. The triggering voltage of the POR circuit is 2.0 ...
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Limiting values Table 50. Absolute maximum ratings In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter V supply voltage CC V input voltage I I latch-up current latchup V electrostatic discharge voltage esd T storage temperature ...
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Static characteristics Table 52. Static characteristics; supply pins +85 C; unless otherwise specified. GND amb Symbol Parameter V regulated supply voltage reg(3.3) I operating supply current CC I suspend supply ...
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Table 54. Static characteristics: analog I/O pins ( Symbol Parameter Input levels V differential input sensitivity DI V differential common mode CM voltage V LOW-level ...
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Dynamic characteristics Table 55. Dynamic characteristics Symbol Parameter Reset t pulse width on input RESET W(RESET) Crystal oscillator f crystal frequency XTAL [1] Dependent on the ...
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GOSUSP WAKEUP SUSPEND CLKOUT T is the bit duration corresponding with the USB data rate. PERIOD Full-speed timing symbols have a subscript prefix ‘F’, low-speed timings a prefix ‘L’. Fig 15. Source differential data-to-EOP transition skew and EOP width. T ...
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Timing 20.1.1 Parallel I/O timing Table 57. Dynamic characteristics: parallel interface timing Symbol Parameter Read timing (see Figure 18) t address hold time after RD HIGH RHAX t address setup time before RD AVRL LOW t data outputs high-impedance ...
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A0 CS/DACK t RLRH RD t RLDV DATA (1) For t , both CS and RD must be deasserted. SHRL Fig 18. Parallel interface read timing (I/O and 8237 compatible DMA AVWL CS/DACK t WLWH WR t DVWH ...
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ALE AD0 DATA Fig 20. ALE timing. 20.1.2 Access cycle timing Table 58. Dynamic characteristics: access cycle timing Symbol Parameter Write command + write data (see T cycle time for write command, cy(WC-WD) then write data T cycle time for ...
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DATA (1) Example: read data. Fig 22. Write data + write command cycle timing. DATA command Fig 23. Write command + read data cycle timing. DATA (1) Example: read data. Fig ...
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Table 59. Dynamic characteristics: single-cycle DMA timing Symbol Parameter Read in DACK-only mode (see Figure t DREQ off after DACK on ASRP t DACK pulse width ASAP DREQ on after DACK off ASAP APRS t data valid ...
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DREQ DACK DATA Fig 26. DMA read timing in DACK-only mode. DREQ DACK DATA Fig 27. DMA write timing in DACK-only mode. DREQ DACK RD/WR (2) EOT (1) t starts from DACK or RD/WR going LOW, whichever occurs later. ASRP ...
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DMA timing: burst mode Table 60. Dynamic characteristics: burst mode DMA timing Symbol Parameter Burst (see Figure 29) t input RD/WR HIGH after RSIH DREQ on t DREQ off after input RD/WR ILRP LOW t DACK off after input ...
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DREQ DACK RD/WR EOT (1) The EOT condition is considered valid if DACK, RD/WR and EOT are all active (= LOW). Fig 30. EOT timing in burst mode DMA. ISP1181B_3 Product data sheet Full-speed USB peripheral controller t ISRP t ...
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Application information 21.1 Typical interface circuits D10 D11 D12 H8S/2357 D13 D14 D15 CSn RD WR IRQ P1.1 DREQ0 DACK TEND (1) 470 assuming that V CC Fig ...
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AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 ALE PSEN 8051 RD WR IRQ P2.3 P2.0 P2.1 BUS_REQ BUS_GNT MCU_WR MCU_RD CS1 CS2 RD WR DREQ DACK EOT DMA CONTROLLER (1) 470 ...
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Interfacing ISP1181B with an H8S/2357 microcontroller This section gives a summary of the ISP1181B interface with a H8S/2357 (or compatible) microcontroller. Aspects discussed are: interrupt handling, address mapping, DMA and I/O port usage for suspend and remote wake-up control. ...
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Using H8S/2357 I/O Ports In the interface circuit of purpose output port. This pin drives the ISP1181B’s WAKEUP input to generate a remote wake-up. The H8S/2357 has 3 registers to configure port 1: Port 1 Data Direction Register (P1DDR), ...
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Package outline TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6 pin 1 index 1 e DIMENSIONS (mm are the original dimensions). A UNIT max. 0.15 ...
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HVQFN48: plastic thermal enhanced very thin quad flat package; no leads; 48 terminals; body 0.85 mm terminal 1 index area terminal 1 48 index area DIMENSIONS (mm are the ...
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Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”. 24.1 Introduction to soldering Soldering ...
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Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see reducing the process window • Solder paste printing issues including smearing, release, ...
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MSL: Moisture Sensitivity Level Fig 36. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. ISP1181B_3 Product data sheet Full-speed USB peripheral controller maximum peak ...
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Revision history Table 63. Revision history Document ID Release date ISP1181B_3 20090123 Modifications: Globally changed Philips Semiconductors and Philips to ST-NXP Wireless. Also updated the legal text. ISP1181B-02 20041207 (9397 750 13958) ISP1181B-01 20020703 (9397 750 09566) ISP1181B_3 Product ...
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Tables Table 1. Ordering information . . . . . . . . . . . . . . . . . . . . .2 Table 2. Pin description . . . . . . . . . ...
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Figures Fig 1. Block diagram Fig 2. Pin configuration TSSOP48 ...
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Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . ...
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Introduction to soldering . . . . . . . . . . . . . . . . . 64 24.2 Wave and reflow soldering . . . . . . . . . . . . . ...
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Information in this document is provided solely in connection with ST-NXP products. ST-NXP Wireless NV and its subsidiaries (“ST-NXP”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at ...