ISP1181BDGG,112 STEricsson, ISP1181BDGG,112 Datasheet - Page 31

• Manufacturer Part Number: ISP1181BDGG,112
• Manufacturer: STEricsson

Specifications of ISP1181BDGG,112

• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Package Type: TSSOP
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / RoHS Status: Supplier Unconfirmed

Table 24.
[1]
ISP1181B_3
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Unchanged by a bus reset.
DMA Configuration Register: bit allocation
12.1.6 Write/Read DMA Configuration
CNTREN
R/W
R/W
0
0
15
7
[1]
[1]
Table 23.
This command defines the DMA configuration of ISP1181B and enables/disables DMA
transfers. The command accesses the DMA Configuration Register, which consists of
2 bytes. The bit allocation is given in
disabled), all other bits remain unchanged.
Code (Hex): F0/F1 — write/read DMA Configuration
Transaction — write/read 2 bytes
Table 25.
Bit
7
6
5
4
3
2
1
0
Bit
15
14
13 to 8
7 to 4
SHORTP
R/W
R/W
0
0
14
6
[1]
[1]
EPDIX[3:0]
Interrupt Enable Register: bit description
DMA Configuration Register: bit description
Symbol
-
SP_IEEOT
IEPSOF
IESOF
IEEOT
IESUSP
IERESM
IERST
Symbol
CNTREN
SHORTP
-
EPDIX[3:0]
R/W
R/W
0
0
13
5
[1]
[1]
Rev. 03 — 23 January 2009
Description
reserved
A logic 1 enables interrupt upon detection of a short packet.
A logic 1 enables 1 ms interrupts upon detection of Pseudo SOF.
A logic 1 enables interrupt upon SOF detection.
A logic 1 enables interrupt upon EOT detection.
A logic 1 enables interrupt upon detection of ‘suspend’ state.
A logic 1 enables interrupt upon detection of a ‘resume’ state.
A logic 1 enables interrupt upon detection of a bus reset.
Description
A logic 1 enables the generation of an EOT condition, when the
DMA Counter Register reaches zero. Bus reset value: unchanged.
A logic 1 enables short/empty packet mode. When receiving (OUT
endpoint) a short/empty packet an EOT condition is generated.
When transmitting (IN endpoint) this bit should be cleared. Bus
reset value: unchanged.
reserved
Indicates the destination endpoint for DMA, see
R/W
R/W
0
0
12
4
[1]
[1]
Table
DMAEN
24. A bus reset will clear bit DMAEN (DMA
R/W
R/W
0
11
3
0
[1]
reserved
Full-speed USB peripheral controller
…continued
reserved
R/W
R/W
0
10
2
0
[1]
© ST-NXP Wireless 2009. All rights reserved.
R/W
R/W
ISP1181B
0
0
9
1
[1]
[1]
BURSTL[1:0]
Table
7.
R/W
R/W
0
0
8
0
30 of 72
[1]
[1]