ISP1181BDGG,112 STEricsson, ISP1181BDGG,112 Datasheet - Page 27

• Manufacturer Part Number: ISP1181BDGG,112
• Manufacturer: STEricsson

Specifications of ISP1181BDGG,112

• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Package Type: TSSOP
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / RoHS Status: Supplier Unconfirmed

Table 14.
Table 16.
ISP1181B_3
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Endpoint Configuration Register: bit allocation
Address Register: bit allocation
12.1.2 Write/Read Device Address
FIFOEN
DEVEN
R/W
R/W
7
0
7
0
Code (Hex): 20 to 2F — write (control OUT, control IN, endpoint 1 to 14)
Code (Hex): 30 to 3F — read (control OUT, control IN, endpoint 1 to 14)
Transaction — write/read 1 byte
Table 15.
This command is used to set the USB assigned address in the Address Register and
enable the USB device. The Address Register bit allocation is shown in
A USB bus reset sets the device address to 00H (internally) and enables the device. The
value of the Address Register (accessible by the micro) is not altered by the bus reset. In
response to the standard USB request Set Address the firmware must issue a Write
Device Address command, followed by sending an empty packet to the host. The new
device address is activated when the host acknowledges the empty packet.
Code (Hex): B6/B7 — write/read Address Register
Transaction — write/read 1 byte
Table 17.
Bit
7
6
5
4
3 to 0
Bit
7
6 to 0
EPDIR
R/W
R/W
6
0
6
0
Endpoint Configuration Register: bit description
Address Register: bit description
Symbol
FIFOEN
EPDIR
DBLBUF
FFOISO
FFOSZ[3:0]
Symbol
DEVEN
DEVADR[6:0]
DBLBUF
R/W
R/W
5
0
5
0
Rev. 03 — 23 January 2009
Description
A logic 1 indicates an enabled FIFO with allocated memory.
A logic 0 indicates a disabled FIFO (no bytes allocated).
This bit defines the endpoint direction (0 = OUT, 1 = IN). It also
determines the DMA transfer direction (0 = read, 1 = write).
A logic 1 indicates that this endpoint has double buffering.
A logic 1 indicates an isochronous endpoint. A logic 0 indicates a
bulk or interrupt endpoint.
Selects the FIFO size according to
Description
A logic 1 enables the device.
This field specifies the USB device address.
FFOISO
R/W
R/W
4
0
4
0
DEVADR[6:0]
R/W
R/W
3
0
3
0
Full-speed USB peripheral controller
R/W
R/W
2
0
2
0
FFOSZ[3:0]
Table 5
© ST-NXP Wireless 2009. All rights reserved.
R/W
R/W
ISP1181B
1
0
1
0
Table
16.
R/W
R/W
0
0
0
0
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