ISP1181BDGG,112 STEricsson, ISP1181BDGG,112 Datasheet - Page 30

• Manufacturer Part Number: ISP1181BDGG,112
• Manufacturer: STEricsson

Specifications of ISP1181BDGG,112

• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Package Type: TSSOP
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / RoHS Status: Supplier Unconfirmed

Table 22.
ISP1181B_3
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Interrupt Enable Register: bit allocation
12.1.5 Write/Read Interrupt Enable Register
reserved
IEP14
IEP6
R/W
R/W
R/W
R/W
31
23
15
0
0
0
7
0
Table 21.
This command is used to individually enable/disable interrupts from all endpoints, as well
as interrupts caused by events on the USB bus (SOF, SOF lost, EOT, suspend, resume,
reset). A bus reset will not change any of the programmed bit values.
The command accesses the Interrupt Enable Register, which consists of 4 bytes. The bit
allocation is given in
Code (Hex): C2/C3 — write/read Interrupt Enable Register
Transaction — write/read 4 bytes
Table 23.
Bit
2
1
0
Bit
31 to 24
23 to 10
9
8
SP_IEEOT
IEP13
IEP5
R/W
R/W
R/W
R/W
30
22
14
0
0
0
6
0
Hardware Configuration Register: bit description
Interrupt Enable Register: bit description
Symbol
PWROFF
INTLVL
INTPOL
Symbol
-
IEP14 to IEP1
IEP0IN
IEP0OUT
IEPSOF
IEP12
IEP4
R/W
R/W
R/W
R/W
29
21
13
0
0
0
5
0
Table
Rev. 03 — 23 January 2009
22.
Description
A logic 1 enables powering-off during ‘suspend’ state. Output
SUSPEND is configured as a power switch control signal for
external devices (HIGH during ‘suspend’). This value should always
be initialized to logic 1. Bus reset value: unchanged.
Selects the interrupt signalling mode on output INT (0 = level,
1 = pulsed). In pulsed mode an interrupt produces an 166 ns pulse.
See
Selects INT signal polarity (0 = active LOW, 1 = active HIGH). Bus
reset value: unchanged.
Description
reserved; must write logic 0
A logic 1 enables interrupts from the indicated endpoint.
A logic 1 enables interrupts from the control IN endpoint.
A logic 1 enables interrupts from the control OUT endpoint.
IESOF
IEP11
IEP3
R/W
R/W
R/W
R/W
Section 13
28
20
12
0
0
0
4
0
reserved
for details. Bus reset value: unchanged.
IEEOT
IEP10
IEP2
R/W
R/W
R/W
R/W
27
19
11
0
0
0
3
0
Full-speed USB peripheral controller
IESUSP
IEP9
IEP1
R/W
R/W
R/W
R/W
26
18
10
0
0
0
2
0
…continued
IERESM
© ST-NXP Wireless 2009. All rights reserved.
IEP0IN
IEP8
R/W
R/W
R/W
R/W
ISP1181B
25
17
0
0
9
0
1
0
IEP0OUT
IERST
IEP7
R/W
R/W
R/W
R/W
24
16
0
0
8
0
0
0
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