ISP1181BDGG,112 STEricsson, ISP1181BDGG,112 Datasheet - Page 61

• Manufacturer Part Number: ISP1181BDGG,112
• Manufacturer: STEricsson

Specifications of ISP1181BDGG,112

• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Package Type: TSSOP
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / RoHS Status: Supplier Unconfirmed

ISP1181B_3
Product data sheet
21.2.1 Interrupt handling
21.2.2 Address mapping in H8S/2357
21.2.3 Using DMA
21.2 Interfacing ISP1181B with an H8S/2357 microcontroller
This section gives a summary of the ISP1181B interface with a H8S/2357 (or compatible)
microcontroller. Aspects discussed are: interrupt handling, address mapping, DMA and
I/O port usage for suspend and remote wake-up control. A typical interface circuit is
shown in
The H8S/2357 bus controller partitions its 16 Mbyte address space into eight areas
(0 to 7) of 2 Mbyte each. The bus controller will activate one of the outputs CS0 to CS7
when external address space for the associated area is accessed.
The ISP1181B can be mapped to any address area, allowing easy interfacing when the
ISP1181B is the only peripheral in that area. If in the example circuit for bus configuration
mode 0 (see
CS7 of the H8S/2357 can be directly connected to input CS of the ISP1181B.
The external bus specifications, bus width, number of access states and number of
program wait states can be programmed for each address area. The recommended
settings of H8S/2357 for interfacing the ISP1181B are:
The ISP1181B can be configured for several methods of DMA with the H8S/2357 and
other devices. The interface circuit in
working with the H8S/2357 in single-address DACK-only DMA mode. External devices
are not shown.
For single-address DACK-only mode, firmware must program the following settings:
•
•
•
•
•
•
ISP1181B: program the Hardware Configuration register to select an active LOW
level for output INT (INTPOL = 0, see
H8S/2357: program the IRQ Sense Control Register (ISCRH and ISCRL) to specify
low-level sensing for the IRQ input.
8-bit bus in Bus Width Control Register (ABWCR)
enable wait states in Access State Control Register (ASTCR)
1 program wait state in the Wait Control Register (WCRH and WCRL).
ISP1181B:
– program the DMA Counter register with the total transfer byte count
– program the Hardware Configuration Register to select active level LOW for DREQ
– select the target endpoint and transfer direction
– select DACK-only mode and enable DMA transfer.
and DACK
Figure
Figure
31.
31) the ISP1181B is mapped to address FFFF08H (in area 7), output
Rev. 03 — 23 January 2009
Figure 31
Table
shows an example of the ISP1181B
20)
Full-speed USB peripheral controller
© ST-NXP Wireless 2009. All rights reserved.
ISP1181B
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