MC9S08GT32ACFDE Freescale, MC9S08GT32ACFDE Datasheet - Page 116

• Manufacturer Part Number: MC9S08GT32ACFDE
• Manufacturer: Freescale

Specifications of MC9S08GT32ACFDE

• Cpu Family: HCS08
• Device Core Size: 8b
• Frequency (max): 40MHz
• Interface Type: I2C/SCI/SPI
• Total Internal Ram Size: 2KB
• # I/os (max): 39
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 1.8/2.08V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 48
• Package Type: QFN EP
• Program Memory Type: Flash
• Program Memory Size: 32KB
• Lead Free Status / RoHS Status: Compliant

Internal Clock Generator (S08ICGV2)
The following sections contain initialization examples for various configurations.
Important configuration information is repeated here for reference.
116
1
The IRG typically consumes 100 μA. The FLL and DCO typically consumes 0.5 to 2.5 mA, depending upon output frequency.
For minimum power consumption and minimum jitter, choose N and R to be as small as possible.
Bypassed
Engaged
1
SCM — self-clocked mode (FLL bypassed
internal)
FBE — FLL bypassed external
FEI — FLL engaged internal
FEE — FLL engaged external
FLL
FLL
Ensure that
Hexadecimal values designated by a preceding $, binary values designated
by a preceding %, and decimal values have no preceding character.
FEI
4 MHz < f
Medium power (will be less than FEE if oscillator
range = high)
Medium clock accuracy (After IRG is trimmed)
Lowest system cost (no external components
required)
IRG is on. DCO is on.
SCM
This mode is mainly provided for quick and reliable
system startup.
3 MHz < f
3 MHz < f
Medium power
Poor accuracy.
IRG is off. DCO is on and open loop.
Clock Scheme
f
ICGDCLK
Clock Reference Source = Internal
Bus
Bus
Bus
, which is equal to
< 20 MHz.
< 5 MHz (default).
< 20 MHz (via filter bits).
Table 7-4. ICGOUT Frequency Calculation Options
Table 7-3. ICG Configuration Consideration
1
MC9S08GB60A Data Sheet, Rev. 2
f
ICGOUT
(f
IRG
f
ext
f
ICGDCLK
f
/ 7)* 64*N / R
* R, does not exceed f
ICGOUT
f
* P * N / R
ext
NOTE
/ R
/ R
1
Range = 0 ; P = 64
FEE
4 MHz < f
Medium power (will be less than FEI if oscillator
range = low)
Good clock accuracy
Medium/High system cost (crystal, resonator or
external clock source required)
IRG is off. DCO is on.
FBE
f
used.
Lowest power
Highest clock accuracy
Medium/High system cost (Crystal, resonator or
external clock source required)
IRG is off. DCO is off.
Range = 1; P = 1
Bus
range <= 8 MHz when crystal or resonator is
Clock Reference Source = External
ICGDCLKmax.
NA
NA
64
P
Bus
< 20 MHz
Typical f
8 MHz out of reset
Typical f
Freescale Semiconductor
Note
IRG
ICGOUT
= 243 kHz
=