MC9S08GT32ACFDE Freescale, MC9S08GT32ACFDE Datasheet - Page 71

• Manufacturer Part Number: MC9S08GT32ACFDE
• Manufacturer: Freescale

Specifications of MC9S08GT32ACFDE

• Cpu Family: HCS08
• Device Core Size: 8b
• Frequency (max): 40MHz
• Interface Type: I2C/SCI/SPI
• Total Internal Ram Size: 2KB
• # I/os (max): 39
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 1.8/2.08V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 48
• Package Type: QFN EP
• Program Memory Type: Flash
• Program Memory Size: 32KB
• Lead Free Status / RoHS Status: Compliant

5.6
The MC9S08GBxxA/GTxxA includes a system to protect against low voltage conditions to protect
memory contents and control MCU system states during supply voltage variations. The system comprises
a power-on reset (POR) circuit and an LVD circuit with a user selectable trip voltage, either high (V
or low (V
by LVDV in SPMSC2. The LVD is disabled upon entering any of the stop modes unless the LVDSE bit is
set. If LVDSE and LVDE are both set, then the MCU cannot enter stop1 or stop2, and the current
consumption in stop3 with the LVD enabled will be greater.
5.6.1
When power is initially applied to the MCU, or when the supply voltage drops below the V
POR circuit will cause a reset condition. As the supply voltage rises, the LVD circuit will hold the chip in
reset until the supply has risen above the V
following a POR.
5.6.2
The LVD can be configured to generate a reset upon detection of a low voltage condition by setting
LVDRE to 1. After an LVD reset has occurred, the LVD system will hold the MCU in reset until the supply
voltage has risen above the level determined by LVDV. The LVD bit in the SRS register is set following
either an LVD reset or POR.
5.6.3
When a low voltage condition is detected and the LVD circuit is configured for interrupt operation (LVDE
set, LVDIE set, and LVDRE clear), then LVDF will be set and an LVD interrupt will occur.
5.6.4
The LVD system has a low voltage warning flag to indicate to the user that the supply voltage is
approaching, but is still above, the LVD voltage. The LVW does not have an interrupt associated with it.
There are two user selectable trip voltages for the LVW, one high (V
voltage is selected by LVWV in SPMSC2.
5.7
The real-time interrupt function can be used to generate periodic interrupts based on a multiple of the
source clock's period. The RTI has two source clock choices, the external clock input (ICGERCLK) to the
ICG or the RTI's own internal clock. The RTI can be used in run, wait, stop2 and stop3 modes. It is not
available in stop1 mode.
In run and wait modes, only the external clock can be used as the RTI's clock source. In stop2 mode, only
the internal RTI clock can be used. In stop3, either the external clock or internal RTI clock can be used.
When using the external oscillator in stop3 mode, it must be enabled in stop (OSCSTEN = 1) and
Freescale Semiconductor
LVDL
Low-Voltage Detect (LVD) System
Real-Time Interrupt (RTI)
Power-On Reset Operation
LVD Reset Operation
LVD Interrupt Operation
Low-Voltage Warning (LVW)
). The LVD circuit is enabled when LVDE in SPMSC1 is high and the trip voltage is selected
MC9S08GB60A Data Sheet, Rev. 2
LVDL
level. Both the POR bit and the LVD bit in SRS are set
Chapter 5 Resets, Interrupts, and System Configuration
LVWH
) and one low (V
LVWL
POR
). The trip
level, the
LVDH
71
)