MC9S08GT32ACFDE Freescale, MC9S08GT32ACFDE Datasheet - Page 89

• Manufacturer Part Number: MC9S08GT32ACFDE
• Manufacturer: Freescale

Specifications of MC9S08GT32ACFDE

• Cpu Family: HCS08
• Device Core Size: 8b
• Frequency (max): 40MHz
• Interface Type: I2C/SCI/SPI
• Total Internal Ram Size: 2KB
• # I/os (max): 39
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 1.8/2.08V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 48
• Package Type: QFN EP
• Program Memory Type: Flash
• Program Memory Size: 32KB
• Lead Free Status / RoHS Status: Compliant

Freescale Semiconductor
PTAPE[7:0]
PTAD[7:0]
Reset
Reset
Field
Field
7:0
7:0
W
W
R
R
PTAPE7
PTAD7
Port A Data Register Bits — For port A pins that are inputs, reads return the logic level on the pin. For port A
pins that are configured as outputs, reads return the last value written to this register.
Writes are latched into all bits of this register. For port A pins that are configured as outputs, the logic level is
driven out the corresponding MCU pin.
Reset forces PTAD to all 0s, but these 0s are not driven out the corresponding pins because reset also configures
all port pins as high-impedance inputs with pullups disabled.
Pullup Enable for Port A Bits — For port A pins that are inputs, these read/write control bits determine whether
internal pullup devices are enabled provided the corresponding PTADDn is 0. For port A pins that are configured
as outputs, these bits are ignored and the internal pullup devices are disabled. When any of bits 7 through 4 of
port A are enabled as KBI inputs and are configured to detect rising edges/high levels, the pullup enable bits
enable pulldown rather than pullup devices.
0 Internal pullup device disabled.
1 Internal pullup device enabled.
0
0
7
7
PTAPE6
PTAD6
0
0
6
6
Figure 6-10. Pullup Enable for Port A (PTAPE)
Figure 6-9. Port A Data Register (PTAD)
Table 6-2. PTAPE Field Descriptions
PTAPE5
Table 6-1. PTAD Field Descriptions
PTAD5
MC9S08GB60A Data Sheet, Rev. 2
0
0
5
5
PTAPE4
PTAD4
0
0
4
4
Description
Description
PTAPE3
PTAD3
3
0
3
0
PTAPE2
PTAD2
0
0
2
2
Chapter 6 Parallel Input/Output
PTAPE1
PTAD1
0
0
1
1
PTAPE0
PTAD0
0
0
0
0
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