CS5535-UDCF AMD (ADVANCED MICRO DEVICES), CS5535-UDCF Datasheet - Page 178
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CS5535-UDCF
Manufacturer Part Number
CS5535-UDCF
Description
Manufacturer
AMD (ADVANCED MICRO DEVICES)
Datasheet
1.CS5535-UDCF.pdf
(579 pages)
Specifications of CS5535-UDCF
Operating Temperature (min)
0C
Operating Temperature (max)
85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Lead Free Status / RoHS Status
Compliant
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5.17.3.4 Wakeup Events
If the system has been put to Sleep, only preprogrammed
wakeup events can get the system running again. The
PMC contains the controls that allow the system to
respond to the selected wakeup events.
On wakeup from Sleep (not Standby, but Sleep Wakeup)
(see Figure 5-53 on page 174), the PMC immediately de-
asserts SLP_CLK_EN# to turn system clocks back on. It
also re-enables PCI/IDE outputs to allow output drivers to
return to their operational levels. Next it de-asserts
SLEEP_X and SLEEP_Y based on programmable delays.
Alternate SLEEP_X and SLEEP_Y interactions are shown
as dotted lines. Lastly, the PMC, re-enables PCI/IDE inputs
after a programmable delay and de-asserts Sleep
Request. The GLCP starts any on-chip PLLs and waits for
them to become stable. Then the GLCP de-asserts SUSP#
to the processor. When the processor de-asserts SUSPA#,
the GLCP de-asserts Sleep Acknowledge. The PMC
allows the wakeup event to assert a System Control Inter-
rupt (SCI).
After a wakeup event:
a) PCI/IDE outputs are re-enabled after SLP_CLK_EN# is
de-asserted.
b) PCI/IDE inputs are re-enabled at Sleep wakeup or after
a programmable delay. Generally, PCI/IDE inputs are nor-
mally used with a delay and that delay is longer than any
de-assertion delay associated with SLEEP_X and/or
SLEEP_Y. Re-enabling PCI/IDE inputs is generally not
useful at the beginning of a wakeup sequence.
c) Sleep Request is de-asserted at Sleep wakeup or after a
programmable delay. Sleep Request is kept de-asserted
until the PCI/IDE inputs are re-enabled. Generally, the
enable and delay values in PM_SED (PMS I/O Offset 14h)
and PM_IN_SLPCTL (PMS I/O Offset 20h) should always
be the same.
d) If used, SLEEP_X/SLEEP_Y delay should be set to
occur
PM_OUT_SLPCTL
PM_IN_SLPCTL (PMS I/O Offset 20h). If the delays for
SLEEP_X/SLEEP_Y are longer than the PM_IN_SLPCTL
delay, then SLEEP_X/SLEEP_Y de-assert at the same
time as the PCI/IDE inputs are re-enabled.
On wakeup from Standby (not Sleep, but Standby
Wakeup) the PMC asserts WORKING and performs a sys-
tem reset. RESET_OUT# is de-asserted after a program-
mable delay and the normal software start-up sequence
begins. However, early in the sequence, the software
checks the PMC state to determine if waking from Standby
(PMS I/O Offset 54h[0]). If yes, then the system state is
potentially restored from non-volatile storage.
If enabled, WORK_AUX may be asserted before or after
RESET_OUT# is de-asserted.
178
between
the
(PMS
31506B
delays
I/O
Offset
programmed
0Ch)
and
in
5.17.3.5 Fail-Safe Power Off
compliant fail-safe power off button. This logic uncondition-
ally de-asserts the WORKING and WORK_AUX signals if
the On/Off button is held down for a programmable delay.
For ACPI compliance, this delay should be set to four sec-
onds.
5.17.3.6 Wake Events Status and SCI
When enabled, a wake event from the general wake
events register (see Section 6.16.4 "GPIO Interrupt and
PME Registers" on page 479) set its status bit and the
“WAK_STS” bit and causes a system control interrupt
(SCI). The Sleep button, RTC alarm, and power button
when asserted, always set their status bit. They set the
“WAK_STS” bit and generate an SCI only when their
enable bit is set. When overflowed, the PM timer sets its
status bit. This overflow condition does not cause a
wakeup event but if enabled, it generates an SCI. The
event’s status is cleared by writing a one to it.
5.17.4
The PMC state machines support the fundamental hard-
ware states: Power Off, Reset Standby, Working, Sleep,
and Controlled Standby.
• Reset Standby State: From Power Off, reset is applied
• Working State: The Working state can be entered from
• Sleep State: The system initiates the entry to the Sleep
The PMC provides the support logic to implement an ACPI
to the Standby domain by the external input pin
RESET_STAND# or through the Low Voltage Detect
(LVD) circuit. Once reset, and the Skip feature is not
enabled, the Reset Standby state de-asserts WORKING
and WORK_AUX outputs and waits for a Reset Standby
wakeup event. If the Skip feature is enabled, the state
machine will proceed to the working state immediately.
To enable Skip, see the signal description for the
PWR_BUT# in Table 3-9 "GPIOx Available Functions
Descriptions" starting on page 49.
Reset Standby, Sleep, or Controlled Standby states.
Working state is established when Working power is
applied and all system clocks are enabled. Once in this
state, registers and functions in the PMC can be initial-
ized, programmed, enabled/disabled, and the potential
exists for the system to proceed to the Sleep state or
Standby state.
state with a Sleep sequence. Under the Sleep state,
Working and Standby power are maintained. PCI/IDE
inputs are disabled when Sleep Acknowledge asserts.
PCI/IDE outputs are disabled when Sleep Acknowledge
asserts or after a programmable delay. SLEEP_X,
SLEEP_Y, and SLP_CLK_EN# may be asserted if
enabled. A Sleep wakeup event returns the system to
Working state.
AMD Geode™ CS5535 Companion Device Data Book
PMC Power Management States
Power Management Control
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