CS5535-UDCF AMD (ADVANCED MICRO DEVICES), CS5535-UDCF Datasheet - Page 515
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CS5535-UDCF
Manufacturer Part Number
CS5535-UDCF
Description
Manufacturer
AMD (ADVANCED MICRO DEVICES)
Datasheet
1.CS5535-UDCF.pdf
(579 pages)
Specifications of CS5535-UDCF
Operating Temperature (min)
0C
Operating Temperature (max)
85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Lead Free Status / RoHS Status
Compliant
Available stocks
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Manufacturer
Quantity
Price
Part Number:
CS5535-UDCF
Manufacturer:
AMD
Quantity:
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Power Management Controller Register Descriptions
6.18.3.15 PM Thermal-Safe Delay and Enable (PM_TSD)
PMS I/O Offset
Type
Reset Value
Reads always return the value written, except for RSVD bits [29:20].
6.18.3.16 PM Power-Safe Delay and Enable (PM_PSD)
PMS I/O Offset
Type
Reset Value
Reads always return the value written, except for RSVD bits [29:20].
AMD Geode™ CS5535 Companion Device Data Book
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
29:20
19:0
Bit
31
30
Name
THRM_LOCK
THRM_EN
RSVD
THRM_DELAY
44h
R/W
00000000h
48h
R/W
00000000h
RSVD
RSVD
Description
Thermal Lock. After this bit is set, the value in this register can not be changed until
RESET_STAND# is applied.
Thermal Enable. Must be high to enable the thermal alarm function.
Reserved. By convention write 0, but may write anything. Reads return 0 value.
Thermal Delay. If the Thermal Alarm (THRM_ALRM#) input signal is asserted for
THRM_DELAY number of 32 kHz clock edges, then unconditionally de-assert WORK-
ING and WORK_AUX to remove Working power. If THRM_ALRM# is still asserted at
wakeup, hold in Standby state until THRM_ALRM# is de-asserted.
THRM_ALRM# needs to be asserted for at least one 32 kHz clock edge for this func-
tion to work properly. A less than one 32 kHz clock edge pulse on THRM_ALRM# may
not be registered.
The delay restarts if THRM_ALRM# de-asserts and then asserts again. If
THRM_ALRM# is asserted, the delay restarts anytime THRM_DELAY (this bit) is writ-
ten.
Since the thermal alarm resides in the Working domain, the THRM_ALRM# input sig-
nal is blocked (de-asserted) when in Standby state. The result is the Standby state
could not be held if the thermal alarm is still asserted at wakeup. Once out of Standby,
the thermal alarm again comes into play. If it is still asserted, its timer would start again.
PM_TSD Bit Descriptions
PM_TSD Register Map
PM_PSD Register Map
LOWBAT_DELAY
THRM_DELAY
9
9
8
8
31506B
7
7
6
6
5
5
4
4
3
3
2
2
1
1
515
0
0
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