LSI53C040-160QFP LSI, LSI53C040-160QFP Datasheet - Page 116
LSI53C040-160QFP
Manufacturer Part Number
LSI53C040-160QFP
Description
Manufacturer
LSI
Datasheet
1.LSI53C040-160QFP.pdf
(212 pages)
Specifications of LSI53C040-160QFP
Mounting
Surface Mount
Lead Free Status / RoHS Status
Supplier Unconfirmed
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7-6
Register: 0xFE03
Miscellaneous Control (MCR)
Read/Write
REV[3:0]
LVD_PWRDWN
SISO
TE
ZMODE
Miscellaneous Registers
7
0
REV[3:0]
6
0
Chip Revision (read only)
These bits define the hardware revision number for the
LSI53C040.
LVD Power Down
A value of 1 in this bit powers down the input LVD
transceivers for operation when not in LVD mode.
SCSI Isolation
When set, this bit 3-states and logically disconnects the
LSI53C040 SCSI port from the SCSI bus when in SE
mode (DIFFSENS = V
TolerANT
This bit is used in LVD mode only. Refer to
information regarding when to set this bit.
High Impedance Mode
Setting this bit to 1 effectively 3-states all output and
bidirectional pads.
5
0
®
REV0
Enable
4
0
LVD_PWRDWN
SS
3
0
).
SISO
2
0
TE
Figure 2.3
1
0
ZMODE
0
0
[7:4]
for
3
2
1
0
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