LSI53C040-160QFP LSI, LSI53C040-160QFP Datasheet - Page 203

• Manufacturer Part Number: LSI53C040-160QFP
• Manufacturer: LSI

Specifications of LSI53C040-160QFP

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Supplier Unconfirmed

register bits (Cont.)
assert ATN/
assert BSY/
assert C_D/
assert data bus
assert I_O/
assert MSG/
assert REQ/
assert SEL/
assert SRST
ATN
attention
BB_N
BER
BERR
BSY 4-9,
bus busy
bus error detection
busy
busy error
C_D
checksum error
chip revision
CKSUM
command/data
CTL0
CTL1
current SCSI data bus
current SCSI data high
D[3:0] 5-6,
D[7:0]
data bits
data bus parity
data transfer length
DB[7:0] 4-3,
DBP
DLADR[2:0]
DLCFG
DLSEL
DM
DMA interrupt 4-17, 7-7, 7-14,
DMA mode
DMA source/destination high
DMA source/destination Low
DMA_INT
download configuration select
download ROM address
download serial ROM
DSDH[7:0]
DSDL[7:0]
DSK_RD/ value 5-6,
DSK_WR/ value 5-5,
DTL[7:0]
DWR/ 5-5,
EIEN
enable parity checking
enable parity interrupt
enable reset output
enable serial output 6-5,
ENCL_ACK/ value 5-6,
end of DMA transfer
ENI 6-5,
EOD
EPC
EPI
ERO
4-7
4-6
4-11
4-9
6-8
4-10
4-6
4-9
4-10
8-7
8-8
6-10
6-9
6-8
6-4
4-11
8-6
8-4
6-9
6-7
4-11
4-15
6-4
5-4
6-8
7-7
4-11
4-16
5-7
4-16
5-6
4-8
4-7
4-5
4-5
4-5
4-8
8-6
5-3
4-8
4-8
7-6
4-4
4-9
4-10
6-9
4-5
6-8
4-15
8-7
5-7
4-10
5-6
8-4
4-6
4-3
4-6
4-13
5-7
Index
8-6
6-6
4-16
4-16
8-6
7-15
ES[1:2] 6-5,
ES0 6-5,
EXS0_INT
EXS1_INT
external interrupt enable 6-5, 6-7,
fast blink rate
FBR[1:0]
FIBD[1:0]
first instruction branch destination
high impedance mode
I/O direction
I_O
ICF
IDR[7:0]
IEN
IMR[7:0]
input/output
INT
intermediate clock frequency
interrupt enable
interrupt request active
IOD
IRA
ITF0 control
ITF0 SCL input
ITF0 SCL output
ITF0 SDA input
ITF0 SDA output
ITF1 control
ITF1 SCL input
ITF1 SCL output
ITF1 SDA input
ITF1 SDA output
LA
LAB
last byte sent
last received bit
LBS
lost arbitration 4-4,
LRB/AD0
LVD
LVD_PWRDWN
MB
message
MLI1_[3:0]
MLI1_[7:4]
MLI2_[3:0]
MLI2_[7:4]
MLL0_[3:0] 8-22,
MLL0_[7:4] bits 8-23,
MLL1_[3:0] bits
MLL1_[7:4] bits
MLL2_[3:0]
MLL2_[7:4]
MLLM0_[3:0]
MLLM0_[7:4]
MLLM1_[3:0]
MLLM1_[7:4]
MLLM2_[3:0] bits
MLLM2_[7:4]
MLO0_[3A:0A], [3B:0B]
MLO0_[7A:4A], [7B:4B]
MLO1_[3A:0A], [3B:0B]
MLO1_[7A:4A], [7B:4B]
MLO2_[3A:0A], [3B:0B]
MLO2_[7A:4A], [7B:4B]
4-4
4-6
4-9
6-3
4-17
4-15
4-11
4-14
6-8
4-8
8-8
7-15
7-13
6-6
8-7
4-9
6-8
8-4
7-8
7-8
8-27
8-27
8-31
8-32
8-33
8-34
4-9
6-6
4-14
6-10
6-9
8-23
8-24
8-28
8-28
8-33
4-8
8-7
6-10
6-9
8-29
8-29
6-10
6-9
4-15
6-8
7-6
6-10
6-9
6-10
6-9
8-24
8-32
6-8
8-25
7-6
4-11
8-21
8-22
8-25
8-26
8-30
8-31
6-3
8-8
8-4
IX-5