LSI53C040-160QFP LSI, LSI53C040-160QFP Datasheet - Page 98

• Manufacturer Part Number: LSI53C040-160QFP
• Manufacturer: LSI

Specifications of LSI53C040-160QFP

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Supplier Unconfirmed

5-6
RD/
ACK/
D[3:0]
Register: 0xFC25/0xFC2D
Manual Data Output (MDATA0/MDATA1)
Read/Write
The values in these registers are asserted onto the SFF-8067 bus when
the PME bit is set in the PCSTx registers (0xFC22/0xFC2A). These
signals are open drain on the SFF-8067 bus. Therefore, a 1 written to
this register is considered a “soft” value and can be pulled low by another
device on the bus.
PESI/
DWR/
SFF-8067 Registers
PESI/
7
1
DWR/
6
1
DSK_RD/ Value
Reading this active low bit gives the state of the
DSK_RD/ signal on the SFF-8067 interface. When this
active low bit is cleared, the drive is ready to read data
from the LSI53C040. It will be cleared (0) if the PESI/ bit
is cleared (0). If PESI/ is 1, this bit reflects the value of
the PA5 signal.
ENCL_ACK/ Value
Reading this active low bit gives the state of the
ENCL_ACK/ signal on the SFF-8067 interface. It will be
cleared (0) if the PESI/ bit is cleared (0). If PESI/ is 1, this
bit reflects the value of the PA4 signal.
8067 Interface Data Nibble Bits
Reading these bits gives the contents of the D[3:0]
signals on the SFF-8067 interface. If PESI/ is 1, these
bits reflect the value of the PA[3:0] signals.
PARALLEL_ESI/ Value
This active low bit is used to change the state of the
PESI/ signal, which is used to select between the SEL_ID
and the bidirectional interface that distinguishes the
SFF-8067 interface from SFF-8045.
DSK_WR/ Value
When this active low bit is cleared, the drive is ready to
write data to the LSI53C040.
RD/
5
1
ACK/
4
1
D3
3
1
D2
2
1
D1
1
1
D0
0
1
[3:0]
5
4
7
6