LSI53C040-160QFP LSI, LSI53C040-160QFP Datasheet - Page 45

• Manufacturer Part Number: LSI53C040-160QFP
• Manufacturer: LSI

Specifications of LSI53C040-160QFP

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Supplier Unconfirmed

2.10 Interrupts
2.10.1 Microcontroller Interrupts
The LSI53C040 supports the following type of interrupts:
The microcontroller core has two interrupt inputs through which interrupt
requests are presented. The SCSI core, DMA core, the Two-Wire Serial
cores, the two timers, the two SFF-8067 ports, and the two external
interrupt ports all generate interrupts that can be individually routed to
either of the two internal interrupt ports of the microcontroller core. The
MPIO3_[1:0] pins are used as the external interrupt lines. Refer to these
pin descriptions for additional information. The
register (0xFE04), allows the LSI53C040 to quickly determine the source
of an interrupt. The
corresponding interrupts in the ISR to be masked by writing a 0 to the
bit location. All interrupts are disabled by default. The
Destination (IDR)
of the ISR to be routed to either of the two interrupt inputs of the
microcontroller core.
During DMA operation, the Two-Wire Serial interrupts and the Timer 2
interrupts should be masked from the microcontroller core so it will not
be interrupted until the DMA transfer is complete or interrupted by the
SCSI core or Timer 1. Other interrupts can also bring the microcontroller
core out of idle mode, but only if they occur during the DMA operation.
Table 2.5
detecting and handling interrupts. The DMA core will pass any SCSI
interrupt along to the microcontroller.
Interrupts
Microcontroller
DMA and SCSI
SFF-8067
Two-Wire Serial
Masking and Enabling
Polling and Hardware
summarizes the primary registers and bits that are used in
register (0xFE0E), allows the corresponding interrupts
Interrupt Mask (IMR)
register (0xFE0D), allows the
Interrupt Status (ISR)
Interrupt
2-27