LSI53C040-160QFP LSI, LSI53C040-160QFP Datasheet - Page 82

• Manufacturer Part Number: LSI53C040-160QFP
• Manufacturer: LSI

Specifications of LSI53C040-160QFP

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Supplier Unconfirmed

4-8
Register: 0xFC03
Target Command (TC)
Read/Write
When connected as a target device, the Target Command register allows
the microcontroller to control the SCSI bus information transfer phase
and/or to assert REQ/ simply by writing this register. The Target Mode
bit (register 0xFC02, bit 6) must be set (1) for bus assertion to occur.
When connected as an initiator with DMA Mode true, if the phase lines
(I_O/, C_D/, and MSG/) do not match the phase bits in this register, a
phase mismatch interrupt is generated when REQ/ goes active. In order
to send data as an initiator, the Assert I_O/, Assert C_D/ and Assert
MSG/ bits must match the corresponding bits in the
Status (CSBS)
meaning when the LSI53C040 is operating as an initiator.
LBS
R
AREQ
AMSG
ACD
AIO
SCSI and DMA Registers
LBS
7
0
6
0
Last Byte Sent
In initiator mode, the SCSI core uses this bit to determine
when the last byte of a DMA transfer is sent to the SCSI
bus. This flag is necessary since the End of DMA bit in
the
last byte was received from the DMA function.
Reserved
Assert REQ/
Assert MSG/
Assert C_D/
Assert I_O/
These bits, when read together, give the current SCSI
bus phase.
correspond to all possible values of these bits.
register (0xFC04). The Assert REQ/ bit (bit 3) has no
Bus and Status (BSR)
R
0
Table 4.2
4
0
describes the SCSI bus phases that
AREQ
3
0
register only reflects when the
AMSG
2
0
Current SCSI Bus
ACD
1
0
AIO
0
0
[6:4]
7
3
2
1
0