LSI53C040-160QFP LSI, LSI53C040-160QFP Datasheet - Page 30

• Manufacturer Part Number: LSI53C040-160QFP
• Manufacturer: LSI

Specifications of LSI53C040-160QFP

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Supplier Unconfirmed

Figure 2.6
Enable Parity Checking, Enable Parity
2-12
Interrupts May Be Set at this Time
MSG/, and C_D/ Bits
Write to Start DMA
Reset Assert I_O/,
Register (0xFC06)
(0xFC03 Bits [2:0]
(Data Out Phase)
Target Receive
Target Receive
DMA Target Mode Transfers
Functional Description
Destination Addresses
(0xFE0D) to Enable
only DMA Interrupts
to 0xFC12, 0xFC13
Register (0xFC11)
(0xFC02 Bits 6, 1)
Length to DTL
Write Transfer
Set TIP Bit In
0xFC10 Bit 0
Write Source/
Set DM, and
TGTM Bits
Write IMR
A
(Reg. 0xFC01, Bit 0)
Write to DMA Send
Set Assert I_O Bit
Register (0xFC05)
(0xFC03 Bits [2:0]
(Data In Phase)
Target Send
Set ADB Bit
Reset C_D/
and MSG/
Wait for an Interrupt
Necessary Interrupts
ISR - Clear Interrupt
Set Bit 1 in Register
That Were Disabled
Power Down Mode
Core to Put It into
for DMA Transfer
Microprocessor
(0xFC02 Bit 1)
(0xFC10 Bit 3)
(0xFC01 Bit 0)
Enable Other
Reset Assert
Data Bus Bit
TC Bit Set?
Reset DMA
0x87 of the
(0xFC0E)
Mode Bit
Interrupt
DMA
A
?
Yes
Yes
No
Target Send Only
Error Recovery