LSI53C040-160QFP LSI, LSI53C040-160QFP Datasheet - Page 118

• Manufacturer Part Number: LSI53C040-160QFP
• Manufacturer: LSI

Specifications of LSI53C040-160QFP

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Supplier Unconfirmed

7-8
EXS1_INT
EXS0_INT
Register: 0xFE05
Timer 1 Control (T1C)
Read/Write
The LSI53C040 includes two built-in timers that run independently of the
microcontroller core. Each timer can be programmed to generate one of
the two possible interrupts to the microcontroller core, as long as these
interrupts are not masked in the
operation will also be suspended if either timer expires and generates an
interrupt to the microcontroller. This frees the internal memory bus to
allow access by the microcontroller after the interrupt awakens the
microcontroller core.
T1EXP
T1RUN
Miscellaneous Registers
T1EXP
7
0
T1RUN
6
0
8067 Port 1 Interrupt or MPIO3_1 Interrupt
A value of 1 in this bit indicates an interrupt pending from
the SFF-8067 port 1 block or an external interrupt
received on MPIO3(1). The bit goes to 0 when the
interrupt is cleared from MPIO3(1) or cleared from the
SFF-8067 port 1 block.
8067 Port 0 Interrupt or MPIO3_0 Interrupt
A value of 1 in this bit indicates an interrupt pending from
the SFF-8067 port 0 block or a external interrupt received
on MPIO3(0). The bit goes to 0 when the interrupt is
cleared from MPIO3(0) or cleared from the SFF-8067
port 0 block.
Timer 1 Expired
A value of 1 in the T1EXP bit indicates that the timer has
expired and an interrupt has been generated, if the
T1IEN bit was set at the time the timer expired. The
interrupt can be cleared by setting the T1CLR bit.
Timer 1 Run
A value of 1 in the T1RUN bit allows the timer to advance.
A value of 0 stops timer advancement.
T1CLR
5
0
T1PS
4
0
Interrupt Mask (IMR)
3
x
R
x
register. Any DMA
1
x
T1IEN
0
0
1
0
7
6