LSI53C040-160QFP LSI, LSI53C040-160QFP Datasheet - Page 84

• Manufacturer Part Number: LSI53C040-160QFP
• Manufacturer: LSI

Specifications of LSI53C040-160QFP

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Supplier Unconfirmed

4-10
SEL
DBP
Register: 0xFC04
Select Enable (SER)
Write Only
SE
Register: 0xFC05
Bus and Status (BSR)
Read Only
The Bus and Status register is a read only register that can be used to
monitor the remaining SCSI control signals not found in the
Bus Status (CSBS)
bits.
EOD
SCSI and DMA Registers
EOD
7
x
7
0
x
R
6
0
Select
Data Bus Parity
Selection ID bits
The Select Enable register is a write only register that is
used as a mask to monitor a single ID during a selection
attempt. The simultaneous occurrence of the
corresponding ID bit, BSY/ false and SEL/ true will cause
an interrupt. This interrupt can be disabled by resetting all
bits in this register and in the
register (0xFC0C). If the Enable Parity Checking bit
(register 0xFC02, bit 5) is active (1), parity will be
checked during selection.
End of DMA Transfer
The End of DMA Transfer bit is set when a DMA transfer
completes. The REQ/ and ACK/ signals should be
monitored to ensure that the last byte has been
transferred. This bit is reset when the DMA Mode bit is
reset (0) in the
register (ATN/ and ACK/), as well as six other status
PERR
x
5
0
IRA
x
4
0
Mode (MR)
SE
PMATCH
x
3
x
register (0xFC02).
Select Enable High (SENHI)
BERR
x
2
0
SATN/
ATN
1
x
Current SCSI
SACK/
ACK
0
x
0
[7:0]
1
0
7