TS8388BMFS9NB1 E2V, TS8388BMFS9NB1 Datasheet - Page 18

• Manufacturer Part Number: TS8388BMFS9NB1
• Manufacturer: E2V

Specifications of TS8388BMFS9NB1

• Lead Free Status / RoHS Status: Supplier Unconfirmed

0973D–BDC–02/09
Application Information
4.8
4-4
e2v semiconductors SAS 2009
Data Ready
Output Signal
Reset
Figure 4-3. Transistor VBE Forward Voltage Versus Junction Temperature (I = 3 mA)
A subvis connector is provided for DRRB command.
The Data ready signal is reset on falling edge of DRRB input command, on ECL logical
low level (-1.8V). DRRB may also be tied to V
master Reset. As long DRRB as remains at logical low level, (or tied to V
Data Ready output remains at logical zero and is independent of the external free run-
ning encoding clock.
The Data ready output signal (DR, DRB) is reset to logical zero after TRDR = 720 ps
typical.
TRDR is measured between the -1.3V point of the falling edge of DRRB input command
and the zero crossing point of the differential Data Ready output signal (DR, DRB).
The Data ready Reset command may be a pulse of 1 ns minimum time width.
The Data ready output signal restarts on DRRB command rising edge, ECL logical high
levels (-0.8V).
DRRB may also be grounded, or is allowed to float, for normal free running Data ready
output signal.
1000
960
920
880
840
800
760
720
680
640
600
-80
-60
-40
-20
Junction temperature (°C)
0
20
TSEV8388B - Evaluation Board User Guide
EE
40
= -5V for Data Ready output signal
60
80
100
EE
120
= -5V), the
140