SI5317C-C-GMR Silicon Laboratories Inc, SI5317C-C-GMR Datasheet
SI5317C-C-GMR
Specifications of SI5317C-C-GMR
Related parts for SI5317C-C-GMR
SI5317C-C-GMR Summary of contents
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ONTR OLLED Features Provides jitter attenuation on any frequency One clock input / two clock outputs Input/output frequency range: 1–710 MHz Ultra low jitter: 300 fs (12 kHz–20 MHz) typical Simple ...
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Si5317 2 Rev. 1.0 ...
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T C ABLE O F ONTENTS Section 1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Si5317 1. Electrical Specifications Table 1. Recommended Operating Conditions (V = 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10 Parameter Symbol Temperature Range T A Supply Voltage V DD Note: All minimum and maximum specifications are guaranteed and ...
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Table 2. DC Characteristics (Continued 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10 Parameter Symbol Differential Input V Voltage Swing 1 CKOUT Output Clock Common Mode V OCM Differential Output Swing V OD Single-ended Output Swing ...
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Si5317 Table 2. DC Characteristics (Continued 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10 Parameter Symbol Input Voltage High V Input Low Current I Input High Current I Weak Internal Input Pull-up R PUP Resistor Weak ...
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Table 2. DC Characteristics (Continued 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10 Parameter Symbol LVCMOS Output Pins Output Voltage Low V Output Voltage High V OH Single-Ended Reference Clock Input Pin XA (XB with cap ...
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Si5317 DOUT, CLOUT Figure 2. Rise/Fall Time Characteristics Rev. 1.0 80% 20% ...
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Three-Level (3L) Input Pins (No External Resistors) External Driver 1.2. Three-Level Input Pins (Example with External Resistors) External Driver One of eight resistors from a Panasonic EXB -D10C183J (or similar) resistor pack Table 3. Three-Level Input Pins Parameter Input ...
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Si5317 Table 4. AC Characteristics (V = 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10 Parameter Input Frequency CKIN Input Pins Input Duty Cycle (Minimum Pulse Width) Input Capacitance Input Rise/Fall Time CKOUT Output Pins Output Frequency (Output ...
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Table 4. AC Characteristics (Continued 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10 Parameter LVCMOS Output Pins Rise/Fall Times LOSn Trigger Window Time to Clear LOL after LOS Cleared t PLL Performance Lock Time Closed Loop ...
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Si5317 Table 5. Performance Specifications (V = 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10 Parameter Symbol Jitter Generation J GEN 622.08 MHz, IN OUT LVPECL output format BW = 120 Hz Phase Noise ...
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Table 6. Thermal Characteristics (V = 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10 Parameter Symbol Thermal Resistance JA Junction to Ambient Thermal Resistance JC Junction to Case Table 7. Absolute Maximum Ratings Parameter DC Supply ...
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Si5317 2. Functional Description 2 CKIN+ CKIN– LOS Alarms LOL Control RST Bandwidth BWSEL[1:0] Control FRQSEL[3:0] Frequency Control FRQTBL INC Skew Control DEC 2.1. Overview The Si5317 is a 1:1 jitter-attenuating precision clock for applications requiring sub 1 ps jitter ...
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Frequency Plan Tables For ease of use, the Si5317 is pin-controlled to enable simple device configuration of the frequency range plan and PLL loop bandwidth via a predefined look-up table. The DSPLL has been optimized for jitter performance and ...
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Si5317 Table 8. Look-up Tables for Fin = Fout Frequency Range and Plan FRQTBL FRQSEL Min No [3: LLLL . LLLM 1. LLLH 1. LLML 1. LLMM 1. ...
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Table 8. Look-up Tables for Fin = Fout Frequency Range and Loop Bandwidth Settings (Continued) Frequency Range Plan FRQTBL FRQSEL Min Center No [3: MLHM 3. MLHH 3. MMLL 3. MMLM 3.60 ...
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Si5317 Table 8. Look-up Tables for Fin = Fout Frequency Range and Loop Bandwidth Settings (Continued) Plan FRQTBL FRQSEL Min No [3: HMMH 10. HMHL 11. HMHM 11. HMHH 12. ...
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Table 8. Look-up Tables for Fin = Fout Frequency Range and Loop Bandwidth Settings (Continued) Frequency Range Plan FRQTBL FRQSEL Min Center No [3:0] 102 M LHML 35.00 103 M LHMM 36.00 104 M LHMH 37.00 105 M LHHL 38.00 ...
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Si5317 Table 8. Look-up Tables for Fin = Fout Frequency Range and Loop Bandwidth Settings (Continued) Plan FRQTBL FRQSEL Min No [3:0] 136 M HLLM 115.00 120.00 125.00 137 M HLLH 120.00 125.00 130.00 138 M HLML 125.00 130.00 135.00 ...
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Table 8. Look-up Tables for Fin = Fout Frequency Range and Loop Bandwidth Settings (Continued) Frequency Range Plan FRQTBL FRQSEL Min Center No [3:0] 169 H LLHM 360.00 370.00 380.00 170 H LLHH 370.00 380.00 390.00 171 H LMLL 380.00 ...
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Si5317 3.3. PLL Self-Calibration An internal self-calibration (ICAL) is performed before operation to optimize loop parameters and jitter performance. While the self-calibration is being performed, the DSPLL is being internally controlled by the self- calibration state machine. The LOL alarm ...
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Alarms Summary alarms are available to indicate the overall status of the input signals. Alarm outputs stay high until all the alarm conditions for that alarm output are cleared. 3.4.1. Loss-of-Signal The device has loss-of-signal circuitry that continuously monitors ...
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Si5317 3.6. PLL Bypass Mode The Si5317 supports a PLL bypass mode in which the selected input clock is fed directly to both enabled output buffers, bypassing the DSPLL. Internally, the bypass path is implemented with high-speed signaling; however, this ...
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High-Speed I/O 4.1. Input Clock Buffer The Si5317 provides differential inputs for the CKIN clock input. This input is internally biased to a common mode voltage (see Table 2, “DC Characteristics”) and can be driven by either a single-ended ...
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Si5317 CML/ LVDS Driver Figure 9. CML/LVDS Termination (1.8, 2.5, 3.3 V) CMOS Driver ohms V R2 Notes DD 3.3 V 100 ohm Locate R1 near CMOS driver 2.5 V 49.9 ohm Locate other components near ...
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Output Clock Driver The Si5317 has a flexible output driver structure that can drive a variety of loads, including LVPECL, LVDS, CML, and CMOS formats. The signal format is selected for CKOUT output using the SFOUT [1:0] pins. This ...
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Si5317 SFOUT[1: (Output disable) Output from DSPLL The SFOUT [1:0] pins can also be used to disable both outputs. Disabling the output puts the CKOUT+ and CKOUT– pins in a high-impedance state relative to V connected to each ...
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Crystal/Reference Clock Input The device can use an external crystal or external clock as a reference external clock is used, it must be ac coupled. With appropriate buffers, the same external reference clock can be applied to ...
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Si5317 5.1. Crystal/Reference Clock Selection An external low-jitter clock or a low-cost crystal is used as part of a fixed-frequency oscillator within the DSPLL. This external clock is required for the device to perform jitter attenuation. Silicon Laboratories recommends using ...
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Table 14. XA/XB Reference Sources and Frequencies RATE[1:0] Type HH Reserved HM Reserved HL Reserved MH External clock MM 3rd overtone crystal ML Reserved LH Reserved LM External clock LL Reserved Because the crystal is used as a jitter reference, ...
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Si5317 5.1.3. Jitter Attenuation Performance The internal VCO uses the XA/XB clock on the XA/XB pins as its reference for jitter attenuation. The XA/XB pins support either a crystal input or an input buffer single-ended or differential clock input, such ...
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Reference Clock Frequency Based on the application and desired output frequency, care should be exercised in selecting the frequency on the reference used for XA/XB. When the CKOUT operating frequency is close to having a simple integer relationship, significant ...
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Si5317 6. Power Supply Filtering This device incorporates an on-chip voltage regulator to power the device from supply voltages of 1.8, 2.5, or 3.3 V. Internal core circuitry is driven from the output of this regulator while I/O circuitry uses ...
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Typical Phase Noise Plots The following is a typical phase noise plot. The clock input source was a Rohde and Schwarz model SML03 RF Generator. The phase noise analyzer was an Agilent model E5052B. The Si5317 operates at 3.3 ...
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Si5317 8. Typical Application Circuit System Power Supply 130 130 1 Input Clock 82 82 Option 1: Crystal Option 2: 0.1 µF Ext. Refclk+ 0.1 µF Ext. Refclk– ...
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Pin Descriptions: Si5317 FRQTBL Note: Pin assignments are preliminary and subject to change. Pin # Pin Name I/O 1 RST FRQTBL 3 LOS ...
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Si5317 Table 15. Si5317 Pin Descriptions (Continued) Pin # Pin Name I 8,31 GND GND 11 RATE0 I 15 RATE1 14 DBL2_BY I 16 CKIN CKIN– 18 LOL O 19 DEC I 20 ...
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Table 15. Si5317 Pin Descriptions (Continued) Pin # Pin Name I/O Signal Level 23 BWSEL1 I 22 BWSEL0 27 FRQSEL3 26 FRQSEL2 25 FRQSEL1 24 FRQSEL0 29 CKOUT1– CKOUT1+ 33 SFOUT0 I 30 SFOUT1 34 CKOUT2– ...
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Si5317 Table 15. Si5317 Pin Descriptions (Continued) Pin # Pin Name I/O 4,9,12,13, NC — 21,36 GND PAD GND GND *Note: LVPECL requires VDD > 2. Signal Level — No Connect. Leave floating. Make no external connections to ...
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... Ordering Guide Ordering Part Number Output Clock Freq Range Si5317A-C-GM 1–710 MHz Si5317B-C-GM 1–350 MHz Si5317C-C-GM 1–200 MHz Si5317D-C-GM 1–100 MHz Si5317-EVB 1–710 MHz Note: Add an “R” at the end of the device to denote tape and reel options (i.e., Si5317A-C-GMR). Table 17. DSPLL Precision Clock Product Selection Guide ...
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Si5317 11. Package Outline: 36-Pin QFN Figure 23 illustrates the package details for the Si5317. Table 18 lists the values for the dimensions shown in the illustration. Figure 23. 36-Pin Quad Flat No-Lead (QFN) Symbol Millimeters Min A 0.80 ...
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Recommended PCB Layout Figure 25. Ground Pad Recommended Layout Figure 24. PCB Land Pattern Diagram Rev. 1.0 Si5317 43 ...
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Si5317 Table 19. PCB Land Pattern Dimensions Dimension Notes (General): 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing is per the ANSI ...
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Si5317 Device Top Mark Laser Mark Method: 0.80 mm Font Size: Right-Justified Si5317Q Line 1 Marking: C-GM Line 2 Marking: YYWWRF Line 3 Marking: Pin 1 Identifier Line 4 Marking: XXXX Customer Part Number Q = Speed Code: A, ...
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Si5317 OCUMENT HANGE IST Revision 0.1 to Revision 0.15 Updated corresponding sections and pinouts to add CKOUT2, INC/DEC, and DBL2_BY functionality. Updated functional block diagram on page 1. Updated Table 2 IDD (DD is subscript). ...
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N : OTES Rev. 1.0 Si5317 47 ...
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