SI5317C-C-GMR Silicon Laboratories Inc, SI5317C-C-GMR Datasheet - Page 24

• Manufacturer Part Number: SI5317C-C-GMR
• Manufacturer: Silicon Laboratories Inc

Specifications of SI5317C-C-GMR

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Si5317
3.6. PLL Bypass Mode
The Si5317 supports a PLL bypass mode in which the selected input clock is fed directly to both enabled output
buffers, bypassing the DSPLL. Internally, the bypass path is implemented with high-speed signaling; however, this
path is not a low jitter path and will result in significantly higher jitter on CKOUT. In PLL bypass mode, the input and
output clocks will be at the same frequency. PLL bypass mode is useful as a debug tool. The DSBL2_BY pin is
used to select the PLL Bypass Mode according to Table 11. Bypass mode is not supported for CMOS clock
outputs.
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FRQSEL[3:0]
BWSEL[1:0]
FRQTBL
CKIN+
CKIN–
DEC
LOS
LOL
RST
INC
2
Skew Control
DSBL2/BYPASS
Bandwidth
Frequency
Control
Control
Control
Alarms
M
H
L
Table 11. DSBL2/BYPASS Pin Settings
f
RATE[1:0]
3
Figure 6. Bypass Signal
External Crystal or
XB
Reference Clock
PLL Bypass Mode w/ CKOUT2 Enabled
DSPLL
Rev. 1.0
®
CKOUT2 Disabled
CKOUT2 Enabled
XA
Function
PLL Bypass
f
OSC
Regulator with
High PSRR
Voltage
0
0
1
1
2
2
VDD (1.8, 2.5, or 3.3 V)
GND
CKOUT+
CKOUT–
DBL2_BY
CKOUT+
CKOUT–
SFOUT[1:0]