SI5317C-C-GMR Silicon Laboratories Inc, SI5317C-C-GMR Datasheet - Page 32

• Manufacturer Part Number: SI5317C-C-GMR
• Manufacturer: Silicon Laboratories Inc

Specifications of SI5317C-C-GMR

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Si5317
5.1.3. Jitter Attenuation Performance
The internal VCO uses the XA/XB clock on the XA/XB pins as its reference for jitter attenuation. The XA/XB pins
support either a crystal input or an input buffer single-ended or differential clock input, such that an external
oscillator can become the reference source. In either case, the device accepts a wide margin in absolute frequency
of the XA/XB input (refer to section 3.5.1. "Recovery from VCO Freeze" on page 23). In VCO freeze, the Si5317's
output clock stability matches the clock supplied on the XA/XB pins. The external crystal or clock must be selected
based on the stability requirements of the application if VCO freeze is a key requirement. However, care must be
exercised in certain areas for optimum performance. For examples of connections to the XA/XB pins, refer to
section 5. Figure 22, “Si5317 Typical Application Circuit,” on page 36.
32
-10
-15
-20
-25
-30
-5
5
0
1
Figure 17. Typical XA-XB Jitter Transfer Function
Jitter Transfer XA/XB Reference to CKOUT
38.88 MHz Clock on XA/XB, RATE[1:0]=LM
10
100
Jitter Frequency (Hz)
Rev. 1.0
1000
10000
100000
1000000