SI5317C-C-GMR Silicon Laboratories Inc, SI5317C-C-GMR Datasheet - Page 12

• Manufacturer Part Number: SI5317C-C-GMR
• Manufacturer: Silicon Laboratories Inc

Specifications of SI5317C-C-GMR

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Si5317
Table 5. Performance Specifications
(V
12
Jitter Generation
LVPECL output format
BW = 120 Hz
Phase Noise
f
LVPECL output format
Notes:
f
IN
IN
DD
= f
1. BWSEL [1:0] loop bandwidth settings provided in Table 9 on page 22.
2. 114.285 MHz 3rd OT crystal used as XA/XB input.
3. V
4. T
5. Test condition: f
= f
= 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10%, T
OUT
OUT
(20-80%), LVPECL clock output.
Parameter
A
DD
= 85 °C
= 622.08 MHz
= 622.08 MHz,
= 2.5 V
IN
= 622.08 MHz, f
Symbol
CKO
J
GEN
PN
OUT
A
= 622.08 MHz, LVPECL clock input: 1.19 Vppd with 0.5 ns rise/fall time
= –40 to 85 ºC)
1, 2, 3, 4, 5
50 kHz–80 MHz
12 kHz–20 MHz
800 Hz–80 MHz
Test Condition
100 kHz offset
10 kHz offset
1 MHz offset
1 kHz offset
Rev. 1.0
Min
—
—
—
—
—
—
—
–132
–132
–106
–121
0.32
0.31
Typ
0.4
–100
–104
–119
Max
0.42
0.41
0.45
–87
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
ps rms
ps rms
ps rms
Unit