SI5317C-C-GMR Silicon Laboratories Inc, SI5317C-C-GMR Datasheet - Page 22

• Manufacturer Part Number: SI5317C-C-GMR
• Manufacturer: Silicon Laboratories Inc

Specifications of SI5317C-C-GMR

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Si5317
3.3. PLL Self-Calibration
An internal self-calibration (ICAL) is performed before operation to optimize loop parameters and jitter
performance. While the self-calibration is being performed, the DSPLL is being internally controlled by the self-
calibration state machine. The LOL alarm will be active during ICAL. The self-calibration time t
Table 4, “AC Characteristics”.
Any of the following events will trigger a self-calibration:




In any of the above cases, an ICAL will be initiated if a valid input clock exists with no input alarm. The external
crystal or reference clock must also be present for the self-calibration to begin. If no valid input clock is present, the
self-calibration state machine will wait until it appears, at which time the calibration will start.
After a successful ICAL has been performed with a valid input clock, no subsequent self-calibrations are performed
unless one of the above conditions are met. If the input clock is lost following self-calibration, the device enters
VCO freeze mode. When the input clock returns, the device relocks to the input clock without performing a self-
calibration.
3.3.1. Input Clock Stability during Internal Self-Calibration
An exit from reset must occur when the selected CKIN clock is stable in frequency with a frequency value that is
within the device operating range.
3.3.2. Self-Calibration caused by Changes in Input Frequency
If the selected CKIN frequency varies by 500 ppm or more within the frequency range defined by FRQSEL and
FRQTBL since the last calibration, the device may initiate a self-calibration.
3.3.3. Device Reset
Upon powerup, the device internally executes a power-on-reset (POR) which resets the internal device logic. The
pin RST can also be used to initiate a reset. The device stays in this state until a valid CKINn is present, when it
then performs a PLL self-calibration (refer to section 3.3. "PLL Self-Calibration”).
3.3.4. Recommended Reset Guidelines
Follow the recommended RESET guidelines in Table 9 that describe when reset should be applied to a device.
22
Power-on-reset (POR)
Release of the external reset pin RST (transition of RST from 0 to 1)
Change in FRQSEL, FRQTBL, BWSEL, or RATE[1:0] pins
Internal DSPLL registers out-of-range, indicating the need to relock the DSPLL
Pin #
15
22
23
24
25
26
27
11
2
Si5317 Pin Name
Table 9. Si5317 Pins and Reset
FRQSEL0
FRQSEL1
FRQSEL2
FRQSEL3
BWSEL0
BWSEL1
FRQTBL
RATE0
RATE1
Rev. 1.0
Must Reset after Changing
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
LOCKHW
is given in