BBT3821-JH Intersil, BBT3821-JH Datasheet - Page 21

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BBT3821-JH

Manufacturer Part Number
BBT3821-JH
Description
IC RE-TIMER OCTAL 192-BGA
Manufacturer
Intersil
Type
Clock and Data Recovery (CDR)r
Datasheet

Specifications of BBT3821-JH

Input
Differential
Output
CML
Frequency - Max
3.1875GHz
Voltage - Supply
1.425 V ~ 1.575 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
192-EBGA
Frequency-max
3.1875GHz
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

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IEEE PMA/PMD REGISTERS (1.0 TO 1.15/1.000F’H)
Note (1): After this RESET bit is written, the BBT3821 will not begin counting PREAMBLE bits immediately. See Figure 17 for details.
Note (1): This bit is latched low on a detected Fault condition. It is set high on being read.
1.0.15
3.0.15
4.0.15
1.0.14
1.0.13
1.0.12
1.0.11
1.0.10:7
1.0.6
1.0.5:2
1.0.1
1.0.0
1.1.15:8
1.1.7
1.1.6:3
1.1.2
1.1.1
1.1.0
1.4.15:3
3.4.15:2
4.4.15:1
1.4.2:1
3.4.1
1.4.0
3.4.0
4.4.0
BIT(S)
BIT
BIT
Reset
Reserved
Speed Select
Reserved
LOPOWER
Reserved
Speed Select
Speed Select
Reserved
PMA Loopback
Reserved
Local Fault
Reserved
Rx Link Up
LoPwrAble
Reserved
Reserved for future
speeds
10PASS-T2/
2BASE-TL
10GbpsAble
NAME
NAME
NAME
21
1 = reset
0 = reset done, normal
operation
1 = 10Gbps
0 = Normal Power
1 = 10Gbps
0000 = 10Gbps
1 = Enable loopback
0 = Normal operation
1 = PMA Local Fault
1 = PMA Rx Link Up
0 = PMA/D Rx Link Down
Low Power Ability
Table 7. IEEE PMA/PMD, PCS, PHY XS, SPEED ABILITY REGISTER
EFM Ability
10Gbps Ablility
MDIO REGISTER ADDRESSES = 1.4, 3.4 & 4.4 ([1,3,4].0004’h)
SETTING
SETTING
SETTING
Table 5. IEEE PMA/PMD CONTROL 1 REGISTER
Table 6. IEEE PMA/PMD STATUS 1 REGISTER
MDIO REGISTER ADDRESS = 1.0 (1.0000’h)
MDIO REGISTER ADDRESS = 1.1 (1.0001’h)
BBT3821
00’h
1’b
0’b
0’h
0’b
0’b
000’h
00’b
1’b
DEFAULT
DEFAULT
0’b
0’b
1’b
0’b
0’b
0’h
1’b
0’h
0’b
0’b
(1)
DEFAULT
RO
RO LL
RO
RO
RO
R/W SC Writing 1 to this bit will reset the whole chip,
RO
R/W
RO
RO
R/W
R/W
R/W
R/W
(1)
including the MDIO registers.
1 = bits 5:2 select speed
No Low Power Mode, writes ignored
1 = bits 5:2 select speed
Operates at 10Gbps
Enable serial loop back mode on all four lanes,
XAUI in to XAUI out.
Device cannot operate @ 2BASE-TL or 10PASS-
T2
Device Able to operate @ 10Gbps
Derived from Register 1.8.11:10
‘Up’ means CX4/LX4 signal level is OK, and the
PLL locked
Device does not support a low power mode
DESCRIPTION
DESCRIPTION
DESCRIPTION
(1)

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