BBT3821-JH Intersil, BBT3821-JH Datasheet - Page 56

• Manufacturer Part Number: BBT3821-JH
• Description: IC RE-TIMER OCTAL 192-BGA
• Manufacturer: Intersil
• Type: Clock and Data Recovery (CDR)r

Specifications of BBT3821-JH

• Input: Differential
• Output: CML
• Frequency - Max: 3.1875GHz
• Voltage - Supply: 1.425 V ~ 1.575 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 192-EBGA
• Frequency-max: 3.1875GHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

P11
R11
R12
T12
P12
N12
T11
N11
P10
B9
A10
N10
D10
A11
B11
D7
D5
D6
N8
C5
A6
A5
A7
B7
D11
PIN#
PIN#
MF[0]
MF[1]
MF[2]
MF[3]
RSTN
BIST_ENA
LX4_MODE
LASI
OPTXLBC
OPTTEMP
OPTXLOP
TX_FAULT
OPRXOP
OPRLOS[3]
OPRLOS[2]
OPRLOS[1]
OPRLOS[0]
XP_ENA
MDIO
MDC
PADR[4]
PADR[3]
PADR[2]
PADR[1]
PADR[0]
NAME
NAME
(1)
(1)
(1)
(1)
(2)
(1)
(1)
(1)
(1)
Output
1.5V CMOS
Input
Input (with pulldown) Built-In Self Test Enable- Active High. When high, enables internal 2
Input (with pulldown) CX4/LX4 Mode Select. When high, LX4 mode is selected. When low, CX4 mode is
Output (open drain)
Input
Input
Input
Input
Input
Input
Input
56
I/O (open drain output)
Input
Input
TYPE
Table 98. MANAGEMENT DATA INTERFACE PINS
TYPE
Multi-function Outputs, Lanes 0 - 3. The functions of these pins are enabled via the MDIO
Interface.
The default condition for these pins is PHY XGXS BIST_ERR. See Table 81 (bits MF_SEL
and MF_CTRL) for further details.
Chip Reset (FIFO Clear) Assert RSTN for at least 10µs from power up. Active low. Schmitt
trigger input, 1.2V CMOS, 2.5V tolerant.
function generator and checker. 1.5V CMOS
selected. This pin decides the trigger sources of LASI, and the default pre-emphasis and
equalization strength of the high speed serial port on the PMA/PMD side. 1.5V CMOS
Link Alarm Status Interrupt Request. When low, pin indicates the existence of an incorrect
condition. An external 10-22kΩ pull-up to 1.2V or 1.5V is recommended. 1.2V CMOS, 2.5V
tolerant.
TX Laser Bias Current. Optical monitoring input. Active level is latched into register bit
1.36868.9 and can be configured to trigger LASI. When this pin is not driven by an external
device, it should be pulled inactive (default down). 1.5V CMOS, 2.5V tolerant.
Transceiver Temperature. Optical monitoring input. Active level is latched into register bit
1.36868.8 and can be configured to trigger LASI. When this pin is not driven by an external
device, it should be pulled inactive (default down). 1.5V CMOS, 2.5V tolerant.
TX Laser Output Power. Optical monitoring input. Active level is latched into register bit
1.36868.7 and can be configured to trigger LASI. When this pin is not driven by an external
device, it should be pulled inactive (default down). 1.5V CMOS, 2.5V tolerant.
TX Fault Condition. Transmitter (Egress) external fault input. Active level is latched into
register bits 1.10 and 1.36868.6 and can be configured to trigger LASI. When this pin is not
driven by an external device, it should be pulled inactive (default down). 1.5V CMOS, 2.5V
tolerant.
Receive Optical Power. Optical monitoring input 4. Active level is latched into register bit
1.36867.5 and can be configured to trigger LASI. When this pin is not driven by an external
device, it should be pulled inactive (default down). 1.5V CMOS, 2.5V tolerant.
Optical Receiver Loss Of Signal. Optical monitoring input 5 – 8. Active (loss) levels are
latched into register 1.10 and can be configured to trigger LASI. When these pins are not
driven by an external device, they should pulled inactive (default down). 1.5V CMOS, 2.5V
tolerant.
XENPAK Enable. Enable XENPAK support. Active high. Activates 2-wire serial bus
interface. 1.5V CMOS, 2.5V tolerant.
Table 99. MISCELLANEOUS PINS
Management Address/Data I/O. 1.2V CMOS input, 2.5V Tolerant
Management Interface Clock. 1.2V CMOS, 2.5V Tolerant, with Schmitt trigger
Management Port Address Setting 1.2V CMOS
BBT3821
DESCRIPTION
DESCRIPTION
23
-1 byte PRBS test