BBT3821-JH Intersil, BBT3821-JH Datasheet - Page 44

• Manufacturer Part Number: BBT3821-JH
• Description: IC RE-TIMER OCTAL 192-BGA
• Manufacturer: Intersil
• Type: Clock and Data Recovery (CDR)r

Specifications of BBT3821-JH

• Input: Differential
• Output: CML
• Frequency - Max: 3.1875GHz
• Voltage - Supply: 1.425 V ~ 1.575 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 192-EBGA
• Frequency-max: 3.1875GHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Note (1): See “BIST Operation” on page 53 for a description of these tests and patterns.
Note (2): This Short pattern is the first 13458 Bytes of the full PRBS 2
Note (3): This pattern is an /S/, preamble, the ‘Short PRBS23’ pattern, one /T/, and 9 /K/s, repeated.
Note (4): A Soft Reset is required to activate the newly selected pattern.
Note (5): The checker expects at least one /K/ on each lane between pattern repeats
3.49161.15:4
4.49161.15:4
3.49161.3
4.49161.3
3.49161.2
4.49161.2
3.49161.1
4.49161.1
3.49161.0
4.49161.0
3.49164.15
3.49164.14:12
3.49164.11
3.49164.10:8
3.49164.7
3.49164.6:4
3.49164.3
3.49164.2:0
BIT
BIT
BIST_EN
Reserved
BIST_DIR
BIST_PAT
BIST_DET
Reserved
BIST_SRC
BIST_CHK
Reserved
HALF_RATE 3
HALF_RATE 2
HALF_RATE 1
HALF_RATE 0
NAME
NAME
44
Table 71. PCS/PHY XS HALF RATE CLOCK CONTROL REGISTER
MDIO REGISTER ADDRESSES = 3.49161 & 4.49161 ([3,4].C009’h)
BIST generator
enable
Select BIST data output
direction
Select BIST
generator data pattern
BIST checker enable
Select BIST data checker
input source
Select BIST
checker data pattern
MDIO REGISTER ADDRESS = 3.49164 (3.C00C’h)
1’b = half rate clock 0’b = full
rate clock
1’b = half rate clock 0’b = full
rate clock
1’b = half rate clock 0’b = full
rate clock
1’b = half rate clock 0’b = full
rate clock
SETTING
Table 72. BIST CONTROL REGISTER
SETTING
23
(5)
(4)
-1 Byte pattern, and also has 9 /K/ per lane as IPG
BBT3821
0’b
0’b
0’h
0’b
0’b
0’h
DEFAULT
0’h
0’b
0’b
0’b
0’b
DEFAULT
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1 = Enable BIST generator
0 = Disable BIST generator
1 = BIST to PCS (transmit path)
0 = BIST to XGXS (receive path)
000 = CRPAT
001 = CJPAT
010 = PRBS23 with 9 /K/s as IPG
011 = Short PRBS23 pattern
100 = Jumbo Ethernet packet
Other = reserved
1 = Enable BIST checker
0 = Disable BIST checker
0 = PCS to BIST (receive path)
1 = XGXS to BIST (transmit path)
000 = CRPAT
001 = CJPAT
010 = PRBS23 with /K/’s as IPG
011 = Short PRBS23 pattern
100 = Jumbo Ethernet packet
Other = reserved
R/W
Lane 3 is running at half rate clock speed
Lane 2 is running at half rate clock speed
Lane 1 is running at half rate clock speed
Lane 0 is running at half rate clock speed
DESCRIPTION
DESCRIPTION
(2)
(2)
(3)
(3)
(1)