BBT3821-JH Intersil, BBT3821-JH Datasheet - Page 50

• Manufacturer Part Number: BBT3821-JH
• Description: IC RE-TIMER OCTAL 192-BGA
• Manufacturer: Intersil
• Type: Clock and Data Recovery (CDR)r

Specifications of BBT3821-JH

• Input: Differential
• Output: CML
• Frequency - Max: 3.1875GHz
• Voltage - Supply: 1.425 V ~ 1.575 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 192-EBGA
• Frequency-max: 3.1875GHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Note (1): The values may be overwritten by the Auto-Configure operation (See “Auto-Configuring Control Registers” on page 16 and Table 92 for details).
Note (1): See Note (2) to Table 42 for a note about the equations and symbols used here.
Note (1): The value may be overwritten by the Auto-Configure operation (See “Auto-Configuring Control Registers” on page 16 and Table 92 for details).
Note (1): These bits are latched high on any Fault condition detected. They are reset low (cleared) on being read. They will also be reset low on reading the LASI
Note (2): See also error counters in registers 3.C00D:E’h (Table 73)
4.49157.15:12
4.49157.11:9
4.49157.8:6
4.49157.5:3
4.49157.2:0
000
001
010
011
4.49158.15:14
4.49158.3:0
4.49159.15:12
4.49159.11
4.49159.10
4.49159.9
4.49159.8
4.49159.7
4.49159.6
4.49159.5
4.49159.4
4.49159.3
4.49159.2
4.49159.1
4.49159.0
ADDRESS
4.C005’h
BITS 2:0
register 1.9004’h (see Table 28)
BIT
BIT
BIT
0
0.17
0.28
0.44
PRE-EMPHASIS
Test Flags
EFIFO_3
EFIFO_2
EFIFO_1
EFIFO_0
Code_3
Code_2
Code_1
Code_0
BIST_ERR_3
BIST_ERR_2
BIST_ERR_1
BIST_ERR_0
(1-V
(802.3ak) =
Reserved
PRE_EMP Lane 3
PRE_EMP Lane 2
PRE_EMP Lane 1
PRE_EMP Lane 0
Reserved
PHY XS
EQ_COEFF
LOW
NAME
NAME
/V
50
HI
NAME
)
(1)
Table 86. PHY XS XAUI PRE-EMPHASIS CONTROL SETTINGS
Table 88. PHY XS RECEIVE PATH TEST AND STATUS FLAGS
0
0.20
0.39
0.79
PRE-EMPHASIS VALUE =
1 = EFIFO error in Lane
0 = no EFIFO error in
Lane
1 = 10b/8b Code error in
Lane
0 = no 10b/8b Code error
1 = BIST error in lane
0 = No BIST error in lane
0’h = no boost in equalizer.
F’h = boost is maximum
MDIO REGISTER ADDRESS = 4.49157 (4.C005’h)
MDIO REGISTER ADDRESS = 4.49158 (4.C006’h)
MDIO REGISTER ADDRESS = 4.49159 (4.C007’h)
Table 85. PHY XS PRE-EMPHASIS CONTROL
Table 87. PHY XS EQUALIZATION CONTROL
(V
HI
SETTING
/ V
See Table 86 for
settings
SETTING
LOW
SETTING
)-1
BBT3821
0’h
0’h
0’h
0’h
0’h
0’b
0’b
0’b
0’b
0’b
0’b
0’b
0’b
0’b
0’b
0’b
0’b
ADDRESS 4.C005’h
100
101
110
111
DEFAULT
DEFAULT
0’h
DEFAULT
BITS 2:0
(1)
ROLH
ROLH
ROLH
ROLH
(1)
R/W
R/W
R/W
R/W
R/W
0.50
0.53
0.57
0.60
Special test use only
PHY XS Elasticity FIFO Overflow/Underflow
Error Detection
PHY XS 10b/8b Decoder Code Violation
Detection
Lane by lane BIST error checker indicator
PRE-EMPHASIS
Configure the level of PHY XS pre-emphasis
(nominal levels indicated)
(1-V
(802.3ak) =
Configuration of the PHY XS equalizer
LOW
(1)
/V
HI
(1)
)
DESCRIPTION
DESCRIPTION
DESCRIPTION
1.00
1.28
1.33
1.50
PRE-EMPHASIS
(V
HI
VALUE =
/ V
LOW
)-1
(1) (2)