BBT3821-JH Intersil, BBT3821-JH Datasheet - Page 64

• Manufacturer Part Number: BBT3821-JH
• Description: IC RE-TIMER OCTAL 192-BGA
• Manufacturer: Intersil
• Type: Clock and Data Recovery (CDR)r

Specifications of BBT3821-JH

• Input: Differential
• Output: CML
• Frequency - Max: 3.1875GHz
• Voltage - Supply: 1.425 V ~ 1.575 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 192-EBGA
• Frequency-max: 3.1875GHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Note (1): The BBT3821 will accept a much higher MDC clock rate and shorter HI and LO times than the IEEE802.3 specification (section 22.2.2.11) requires. Such a
Note (2): The BBT3821 MDIO registers will not be written until two MDC clocks have occurred after the frame end. These will normally count toward the minimum
Note (1): Assuming RFCP-N clock is 156.25MHz, and register bits 1.8005.6:4 set for 400kHz (Table 20). SCL clock period scales with reference clock frequency. Also,
T
T
T
T
T
T
C
MDCD
MDS
MDH
MDC
MDV
Update
MD
SYMBOL
T
T
SYMBOL
SYMBOL
T
T
T
T
SCL_DAV
SDA_CLV
T
T
CLAH_L
RSTBIT
MDRST
RESET
TRAIN
C
faster clock may not be acceptable to other devices on the interface.
preamble before the next frame, except in the case of writing a RESET into [1,3,4].0.15, see
per the I
additional time. Any RC delays on the SCL line will add to the SCL ‘High’ time, in increments of approximately 100ns.
WAIT
I2C
2
C specification, the SCL ‘High’ time is stretched by the time taken for SCL to go high after the BBT3821 releases it, to allow an I
BBT3821 MDIO out delay from MDC
Setup from MDIO in to MDC
Hold from MDC to MDIO in
Clock Period MDC
MDC Clock HI or LO time
Delay from last data bit to register update
Input Capacitance
Reset bit Active width
Delay from Reset bit to first active preamble count
RSTN Active width
Delay from RSTN to I
I
Period of I
Setup from I
Setup, Hold from SDA for START, STOP
Input Capacitance
2
C ‘training’ (external reset)
Table 115. MDIO INTERFACE TIMING (FROM IEEE802.3AE) (SEE Figure 15 TO Figure 17)
Table 117. RESET AND I
64
2
C SCL Clock Line (400kHz)
2
C SDA Data Valid to SCL edge
(1)
(1)
2
PARAMETER
Table 116. RESET AND MDIO TIMING (SEE Figure 17)
C SCL Start
PARAMETER
PARAMETER
2
C SERIAL INTERFACE TIMING (SEE Figure 18 AND Figure 24)
(2)
BBT3821
MIN
MIN
240
100
600
Figure 17
2.5
10
MIN
100
10
10
20
0
.
TYP
TYP
256
10
30
2
TYP
400
160
5.0
1.5
1.5
2
MAX
MAX
282
MAX
10
300
10
2
C slave to demand
T
T
UNITS
REFCLK
UNITS
CLAH_L
T
T
UNIT
µs
MDC
MDC
ms
pF
pF
ns
ns
ns
ns
ns
µs
ns
ns
(1)