BBT3821-JH Intersil, BBT3821-JH Datasheet - Page 40

• Manufacturer Part Number: BBT3821-JH
• Description: IC RE-TIMER OCTAL 192-BGA
• Manufacturer: Intersil
• Type: Clock and Data Recovery (CDR)r

Specifications of BBT3821-JH

• Input: Differential
• Output: CML
• Frequency - Max: 3.1875GHz
• Voltage - Supply: 1.425 V ~ 1.575 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 192-EBGA
• Frequency-max: 3.1875GHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Note (1): These bits are latched high on any Fault condition detected. They are reset low (cleared) on being read. They will also be reset low on reading the LASI
Note (1): The status of these bits depends on the signal conditions. Default shown is for normal operation. The bits contribute to the RX Local Fault bit, see Table 60.
Note (2): See Note (1) to Table 57, Note (2) to Table 64 and/or “PCS (Parallel) Loopback (4.C004.[3:0] & Optionally 3.0.14)” under “Loopback Modes ” on page 13. If
Note (1): For other test pattern generation capabilities incorporated in the BBT3821, including CJPAT and CRPAT, see Table 72.
3.8.15:14
3.8.13:12
3.8.11
3.8.10
3.8.9:3
3.8.2
3.8.1
3.8.0
3.24.15:13
3.24.12
3.24.11
3.24.10
3.24.9:4
3.24.3
3.24.2
3.24.1
3.24.0
3.25.15:3
3.25.2
3.25.1:0
BIT
BIT
BIT
registers 1.9003’h (bit 10, see Table 27) or 1.9004’h (bit 11, see Table 28)
enabled, this register bit does NOT conform to the IEEE 802.3ae-2002 specification.
Device present
Reserved
TX LocalFlt
RX LocalFlt
Reserved
10GBASE-W
10GBASE-X
10GBASE-R
Reserved
Lane_Align
Test_Pattern
PCS Loopback
Ability
Reserved
Reserved
Lane3 Sync
Lane2 Sync
Lane1 Sync
Lane0 Sync
Reserved
PCS TestPatEn
PCS TestPat
Type
NAME
NAME
(2)
NAME
or
Table 60. IEEE PCS STATUS 2 DEVICE PRESENT & FAULT SUMMARY REGISTER
40
Transmit Test Pattern
Enable
Test pattern
select
10 = Device present
1 = TX Local Fault; on Egress
channel
1 = RX Local Fault; on Ingress
channel
0 = cannot perform
1 = can perform
0 = cannot perform
1 = 4 Lanes Aligned
0 = Lanes not aligned
Test Pattern Abilities
1 = has Optional PCS
Loopback Ability.
1 = PCS Lane is Synchronized
0 = PCS Lane not
Synchronized
Table 62. IEEE 10GBASE-X PCS TEST CONTROL REGISTER
SETTING
Table 61. IEEE 10GBASE-X PCS STATUS REGISTER
MDIO REGISTER ADDRESSES = 3.24 (3.0018’h)
SETTING
MDIO REGISTER ADDRESS = 3.25 (3.0019’h)
SETTING
MDIO REGISTER ADDRESS = 3.8 (3.0008’h)
0’b
00’b
DEFAULT
BBT3821
10’b
0’b
0’b
0’b
1’b
0’b
DEFAULT
1’b
1’b
0’b
00’h
1’b
1’b
1’b
1’b
DEFAULT
R/W
R/W
(1)
(1)
(1)
(1)
(1)
R/W
0 = Do not Transmit test pattern
1 = Transmit test pattern
11 = Reserved
10 = Mixed frequency test pattern (Continuous /K/ = K28.5)
01 = Low frequency test pattern (repeat 0000011111 = K28.7)
00 = High frequency test pattern (repeat 0101010101 = D10.2)
RO
RO LH
RO LH
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
R/W
R/W
(1)
(1)
When read as “10”, it indicates that a device is
present at this device address
PLL Lock Failure is only PCS TX Fault
Lane Alignment or Byte Alignment not done, or
Loss of Signal, from Register 3.24 (3.0018’h)
Device cannot be 10GBASE-W
Device can perform 10GBASE-X
Device cannot be 10GBASE-R
1 = All four 3G receive lanes (on ingress path) are
aligned
1 = The device is able to generate test patterns for
10GBASE-X
If enabled by EN_PCS_LB (see bit 3.C001’h.7,
Table 64) indicates PCS Loopback ability, and is a
1‘b bit; otherwise, a reserved 0’b bit
Reflects the PCS_SYNC byte alignment state
machine condition; not valid if not enabled in
device (see Table 63)
DESCRIPTION
DESCRIPTION
DESCRIPTION
(2)
.