ISL12023IVZ Intersil, ISL12023IVZ Datasheet - Page 15

• Manufacturer Part Number: ISL12023IVZ
• Description: IC RTC/CLDR TEMP SNSR 14-TSSOP
• Manufacturer: Intersil
• Type: Clock/Calendarr

Specifications of ISL12023IVZ

• Memory Size: 1K (128 x 8)
• Time Format: HH:MM:SS (12/24 hr)
• Date Format: YY-MM-DD-dd
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 14-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

POWER SUPPLY CONTROL REGISTER (PWR_VDD)
Clear Time Stamp Bit (CLRTS)
This bit clears Time Stamp V
Stamp Battery to V
is 0 (CLRTS = 0) and the Enabled setting is 1 (CLRTS = 1)
V
These bits set the 6 trip levels for the V
that V
LVDD bit in the Status Register is set to “1” and the LVRST
pin is asserted LOW. See Table 6.
Battery Voltage Trip Voltage Register (PWR_VBAT)
This register controls the trip points for the two V
with levels set to approximately 85% and 75% of the nominal
battery level.
09h
TABLE 5. FREQUENCY SELECTION OF F
ADDR
FREQUENCY,
DD
V
DD
F
1024
1/16
1/32
Brownout Trip Voltage BITS (V
DD
OUT
1/2
1/4
1/8
64
32
16
8
4
2
1
0
0
0
0
1
1
Trip2
CLRTS
has dropped below a preset level. In this event, the
7
UNITS
6
0
TABLE 6. VDD TRIP LEVELS
Hz
Hz
Hz
Hz
Hz
Hz
Hz
Hz
Hz
Hz
Hz
Hz
Hz
DD
V
DD
5
0
Registers (TSB2V). The default setting
0
0
1
1
0
0
Trip1
4
0
FO3
0
0
0
0
0
1
1
1
1
1
1
1
1
DD
15
3
0
to Battery (TSV2B) and Time
V
V
DD
DD
FO2
2
Trip2 V
0
1
1
1
1
0
0
0
0
1
1
1
1
0
1
0
1
0
1
Trip0
DD
OUT
DD
alarm, indicating
DD
PIN (Continued)
FO1
Trip<2:0>)
1
0
0
1
1
0
0
1
1
0
0
1
1
1
Trip1 V
BAT
VOLTAGE
2.295
2.550
2.805
3.060
4.250
4.675
TRIP
(V)
alarms,
FO0
DD
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Trip0
ISL12023
RESEAL BIT (RESEALB)
This is the Reseal bit for actively disconnecting V
the internal circuitry. Setting this bit allows the device to
disconnect the battery and eliminate standby current drain
while the device is unused. Once V
reset and the V
circuitry.
BATTERY LEVEL MONITOR TRIP BITS (VB85TP<2:0>)
Three bits selects the first alarm (85% of Nominal V
for the battery voltage monitor. There are total of 7 levels that
could be selected for the first alarm. Any of the of levels could
be selected as the first alarm with no reference as to nominal
Battery voltage level. See Table 8.
BATTERY LEVEL MONITOR TRIP BITS (VB75TP<2:0>)
Three bits select the second alarm (75% of Nominal V
level for the battery voltage monitor. There are total of 7 levels
that could be selected for the second alarm. Any of the of levels
could be selected as the second alarm with no reference as to
nominal Battery voltage level. See Table 9.
ADDR 7
0Ah D RESEALB VB85Tp2 VB85Tp1 VB85Tp0 VB75Tp2 VB75Tp1 VB75Tp0
TABLE 9. BATTERY LEVEL MONITOR TRIP BITS
VB85Tp2
VB75Tp2
0
0
0
0
1
1
1
0
0
0
0
1
1
1
(VB75TP<2:0>)
6
BAT
TABLE 8. VB85T ALARM LEVEL
VB85Tp1
VB75Tp1
pin is then connected to the internal
5
0
0
1
1
0
0
1
0
0
1
1
0
0
1
TABLE 7.
4
VB85Tp0
VB75Tp0
DD
0
1
0
1
0
1
0
0
1
0
1
0
1
0
is powered up, this bit is
3
2
ALARM TRIP
ALARM TRIP
BAT
BATTERY
BATTERY
BAT
LEVEL
LEVEL
2.125
2.295
2.550
2.805
3.060
4.250
4.675
1.875
2.025
2.250
2.475
2.700
3.750
4.125
June 24, 2009
pin from
(V)
(V)
BAT
) level
FN6682.2
1
)
0