ISL12023IVZ Intersil, ISL12023IVZ Datasheet - Page 4

IC RTC/CLDR TEMP SNSR 14-TSSOP

ISL12023IVZ

Manufacturer Part Number
ISL12023IVZ
Description
IC RTC/CLDR TEMP SNSR 14-TSSOP
Manufacturer
Intersil
Type
Clock/Calendarr
Datasheet

Specifications of ISL12023IVZ

Memory Size
1K (128 x 8)
Time Format
HH:MM:SS (12/24 hr)
Date Format
YY-MM-DD-dd
Interface
I²C, 2-Wire Serial
Voltage - Supply
2.7 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
14-TSSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ISL12023IVZ
Manufacturer:
Intersil
Quantity:
341
Power-Down Timing
I
2
Hysteresis
C Interface Specifications
SYMBOL
SYMBOL
t
V
t
t
t
t
HD:DAT
SU:STO
SU:STA
HD:STA
SU:DAT
t
t
DD SR-
C
f
t
HIGH
V
LOW
V
BUF
V
SCL
t
t
PIN
AA
OL
IN
IH
IL
SDA and SCL Input Buffer LOW
Voltage
SDA and SCL Input Buffer HIGH
Voltage
SDA and SCL Input Buffer
Hysteresis
SDA Output Buffer LOW Voltage,
Sinking 3mA
SDA and SCL Pin Capacitance
SCL Frequency
Pulse Width Suppression Time at
SDA and SCL Inputs
SCL Falling Edge To SDA Output
Data Valid
Time the Bus must be Free Before
the Start of a New Transmission
Clock LOW Time
Clock HIGH Time
START Condition Setup Time
START Condition Hold Time
Input Data Setup Time
Input Data Hold Time
STOP Condition Setup Time
V
DD
Negative Slew Rate
PARAMETER
PARAMETER
Test Conditions: V
4
Test Conditions: V
DD
= +2.7 to +5.5V, T
V
T
V
V
Any pulse narrower than the
max spec is suppressed.
SCL falling edge crossing 30%
of V
30% to 70% of V
SDA crossing 70% of V
during a STOP condition, to
SDA crossing 70% of V
during the following START
condition.
Measured at the 30% of V
crossing.
Measured at the 70% of V
crossing.
SCL rising edge to SDA falling
edge. Both crossing 70% of
V
From SDA falling edge
crossing 30% of V
falling edge crossing 70% of
V
From SDA exiting the 30% to
70% of V
rising edge crossing 30% of
V
From SCL falling edge
crossing 30% of V
entering the 30% to 70% of
V
From SCL rising edge
crossing 70% of V
rising edge crossing 30% of
V
A
DD
DD
OUT
DD
DD
DD.
DD
DD
= +25°C, f = 1MHz,
DD
DD
.
.
.
TEST CONDITIONS
= 5V, I
= 5V, V
window.
= 0V
, until SDA exits the
= +2.7 to +5.5V, T
DD
OL
IN
ISL12023
window, to SCL
CONDITIONS
= 3mA
= 0V,
DD
A
DD
DD
DD
= -40°C to +85°C, unless otherwise stated.
window.
, to SDA
to SCL
to SDA
DD
DD
A
DD
DD
= -40°C to +85°C, unless otherwise specified.
0.05 x V
0.7 x V
(Note 9)
1300
1300
MIN
-0.3
600
600
600
100
600
0
0
(Note 9)
DD
MIN
DD
(Note 5)
TYP
0.02
(Note 5)
TYP
0.3 x V
V
(Note 9)
DD
(Note 9)
MAX
400
900
900
MAX
0.4
10
50
10
+ 0.3
DD
UNITS
UNITS
V/ms
kHz
pF
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
V
V
V
V
June 24, 2009
NOTES
NOTES
FN6682.2
7, 8
7, 8
6

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