ISL12023IVZ Intersil, ISL12023IVZ Datasheet - Page 24

• Manufacturer Part Number: ISL12023IVZ
• Description: IC RTC/CLDR TEMP SNSR 14-TSSOP
• Manufacturer: Intersil
• Type: Clock/Calendarr

Specifications of ISL12023IVZ

• Memory Size: 1K (128 x 8)
• Time Format: HH:MM:SS (12/24 hr)
• Date Format: YY-MM-DD-dd
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 14-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

.
After loading the entire Slave Address Byte from the SDA bus,
the ISL12023 compares the device identifier and device select
bits with “1101111” or “1010111”. Upon a correct compare, the
device outputs an acknowledge on the SDA line.
Following the Slave Byte is a one byte word address. The word
address is either supplied by the master device or obtained
from an internal counter. On power-up, the internal address
counter is set to address 00h, so a current address read starts
at address 00h. When required, as part of a random read, the
master must supply the 1 Word Address Bytes, as shown in
Figure 18.
In a random read operation, the slave byte in the “dummy write”
portion must match the slave byte in the “read” section. For a
random read of the Control/Status Registers, the slave byte
must be “1101111x” in both places.
Write Operation
A Write operation requires a START condition, followed by a
valid Identification Byte, a valid Address Byte, a Data Byte,
and a STOP condition. After each of the three bytes, the
ISL12023 responds with an ACK. At this time, the I
interface enters a standby state.
Read Operation
A Read operation consists of a three byte instruction
followed by one or more Data Bytes (see Figure 18). The
master initiates the operation issuing the following
sequence: a START, the Identification byte with the R/W bit
set to “0”, an Address Byte, a second START, and a second
Identification byte with the R/W bit set to “1”. After each of
the three bytes, the ISL12023 responds with an ACK. Then
the ISL12023 transmits Data Bytes as long as the master
FIGURE 17. SLAVE ADDRESS, WORD ADDRESS, AND DATA
A7
D7
1
FROM THE
SIGNALS
MASTER
SIGNALS FROM
SIGNAL AT
A6
D6
1
THE SLAVE
SDA
A5
D5
0
BYTES
S
A
R
T
T
A4
D4
1
1
IDENTIFICATION
1
BYTE WITH
A3
D3
0
1
R/W = 0
1 1 1 1
24
1
A2
D2
FIGURE 18. READ SEQUENCE (CSR SLAVE ADDRESS SHOWN)
0
1
A1
D1
A
C
K
R/W
A0
D0
ADDRESS
BYTE
SLAVE
ADDRESS BYTE
WORD ADDRESS
DATA BYTE
2
C
A
C
K
ISL12023
S
A
R
T
T
IDENTIFICATION
1
BYTE WITH
1
R/W = 1
0
1 1 1 1
responds with an ACK during the SCL cycle following the
eighth bit of each byte. The master terminates the read
operation (issuing a STOP condition) following the last bit of
the last Data Byte (see Figure 18).
The Data Bytes are from the memory location indicated by
an internal pointer. This pointers initial value is determined
by the Address Byte in the Read operation instruction, and
increments by one during transmission of each Data Byte.
After reaching the memory location 2Fh, the pointer “rolls
over” to 00h, and the device continues to output data for
each ACK received.
Application Section
Battery-Backup Details
The ISL12023 has automatic switchover to battery-backup
when the V
variety of backup sources can be used, including standard
and rechargeable lithium, super capacitors, or regulated
secondary sources. The serial interface is disabled in
battery-backup, while the oscillator and RTC registers are
operational. The SRAM register contents are powered to
preserve their contents as well.
The input voltage range for V
mind the temperature compensation only operates for V
> 2.7V. Note that the device is not guaranteed to operate
with a V
discharging to that level. It is strongly advised to monitor the
low battery indicators in the status registers and take action
to replace discharged batteries.
If a supercapacitor is used, it is possible that it may
discharge to below 1.8V during prolonged power-down.
Once powered up, the device may lose serial bus
communications until both V
together. To avoid that situation, including situations where a
battery may discharge deeply, the circuit in Figure 19 can be
used. Some applications will require separate supplies for
the RTC V
may compromise the operation of the I
applications that do require serial bus communication with
the RTC V
low during the time the RTC V
1
BAT
A
C
K
DD
DD
DD
< 1.8V, so the battery should be changed before
FIRST READ
DATA BYTE
and the I
powered down, the SDA pin must be pulled
drops below the V
2
C pull-ups. This is not advised, as it
A
C
K
DD
BAT
DD
and V
BAT
is 1.8V to 5.5V, but keep in
ramps down to 0V.
A
C
K
mode threshold. A wide
BAT
2
LAST READ
DATA BYTE
C bus. For
are powered down
June 24, 2009
FN6682.2
S
O
P
BAT
T