ISL12023IVZ Intersil, ISL12023IVZ Datasheet - Page 16

IC RTC/CLDR TEMP SNSR 14-TSSOP

ISL12023IVZ

Manufacturer Part Number
ISL12023IVZ
Description
IC RTC/CLDR TEMP SNSR 14-TSSOP
Manufacturer
Intersil
Type
Clock/Calendarr
Datasheet

Specifications of ISL12023IVZ

Memory Size
1K (128 x 8)
Time Format
HH:MM:SS (12/24 hr)
Date Format
YY-MM-DD-dd
Interface
I²C, 2-Wire Serial
Voltage - Supply
2.7 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
14-TSSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ISL12023IVZ
Manufacturer:
Intersil
Quantity:
341
Initial AT and DT Setting Register (ITRO)
These bits are used to trim the initial error (at room
temperature) of the crystal. Both Digital Trimming (DT) and
Analog Trimming (AT) methods are available. The digital
trimming uses clock pulse skipping and insertion for
frequency adjustment. Analog trimming uses load
capacitance adjustment to pull the oscillator frequency. A
range of +62.5ppm to -61.5ppm is possible with combined
digital and analog trimming.
AGING AND INITIAL TRIM DIGITAL TRIMMING BITS
(IDTR0<1:0>)
These bits allow ±30.5ppm initial trimming range for the
crystal frequency. This is meant to be a coarse adjustment if
the range needed is outside that of the IATR control. See
Table 10. The IDTR0 register should only be changed while
the TSE (Temp Sense Enable) bit is “0”.
AGING AND INITIAL ANALOG TRIMMING BITS
(IATR0<5:0>)
The analog trimming register allows +32ppm to -31ppm
adjustment in 1ppm/bit increments. This enables fine frequency
adjustment for trimming initial crystal accuracy error or to
correct for aging drift. The IATR0 register should only be
changed while the TSE (Temp Sense Enable) bit is “0”.
Note that setting the IATR to the lowest settings (-31ppm)
with the default 32kHz output can cause the oscillator
frequency to become unstable on power-up. The lowest
settings for IATR should be avoided to insure oscillator
frequency integrity.
ADDR
IATR05 IATR04 IATR03 IATR02 IATR01 IATR00
0Bh
0
0
0
0
0
0
0
0
IDTR01
TABLE 11. INITIAL AT AND DT SETTING REGISTER
0
0
1
1
IDTR01 IDTR00 IATR05 IATR04 IATR03 IATR02 IATR01 IATR00
7
0
0
0
0
0
0
0
0
TABLE 12. IATRO TRIMMING RANGE
TABLE 10. IDTR0 TRIMMING RANGE
6
IDTR00
0
0
0
0
0
0
0
0
0
1
0
1
5
0
0
0
0
1
1
1
1
16
Default/Disabled
+30.5ppm
0ppm
-30.5ppm
4
TRIMMING RANGE
0
0
1
1
0
0
1
1
3
2
0
1
0
1
0
1
0
1
TRIMMING
1
RANGE
+32
+31
+30
+29
+28
+27
+26
+25
0
ISL12023
IATR05 IATR04 IATR03 IATR02 IATR01 IATR00
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
TABLE 12. IATRO TRIMMING RANGE (Continued)
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
TRIMMING
June 24, 2009
RANGE
+24
+23
+22
+21
+20
+19
+18
+17
+16
+15
+14
+13
+12
+10
+11
-10
-11
-12
-13
-14
-15
-16
-17
-18
-19
-20
-21
-22
-23
-24
-25
-26
-27
FN6682.2
+9
+8
+7
+6
+5
+4
+3
+2
+1
-1
-2
-3
-4
-5
-6
-7
-8
-9
0

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