TWR-K60N512-KEIL Freescale Semiconductor, TWR-K60N512-KEIL Datasheet - Page 46

• Manufacturer Part Number: TWR-K60N512-KEIL
• Description: K60N512 Keil Tower Kit
• Manufacturer: Freescale Semiconductor
• Series: Kinetisr
• Type: MCUr

Specifications of TWR-K60N512-KEIL

• Rohs Compliant: YES
• Contents: 4 Boards, Documentation, DVD
• Peak Reflow Compatible (260 C): Yes
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Freescale Tower System, K60N512

Configuration examples
// now move to FBI mode
// set CLKS to 1 to select the internal reference clock
// keep FRDIV at existing value to keep FLL ref clock in spec.
// set IREFS to 1 to select internal reference clock
// wait for internal reference to be selected
// wait for fast internal reference to be selected
// wait for clock to switch to IRC
// now move to BLPI
// set up the SIM clock dividers BEFORE switching to VLPR to ensure the
// system clock speeds are in spec. MCGCLKOUT = 2 MHz in BLPI mode
// core = 2 MHz, bus = 2 MHz, flexbus = 2 MHz, flash = 1 MHz
Now that MCGCLKOUT is at 2 MHz, the MCU VLPR power mode may be selected.
Refer to the power management controller for details on this. When the MCU transitions
back to normal run mode, the MCG will still be configured in BLPI mode. The MCG is
then configured in PLL engaged external mode by means of software as follows:
// Moving from BLPI to PEE
// first move to FBI
// move to FBE
// clear IREFS to select the external ref clock
// set CLKS = 2 to select the ext ref clock as clk source
// it is assumed the oscillator parameters in MCG_C2 have not been changed
// wait for the oscillator to initialize again
// wait for Reference clock to switch to external reference
// wait for MCGOUT to switch over to the external reference clock
//configure PLL and system clock dividers as FEI to PEE example
// configure the clock dividers back again before switching to the PLL to ensure the system
// clock speeds are in spec.
// core = PLL (96MHz), bus = PLL/2 (48MHz), flexbus = PLL/2 (48MHz), flash = PLL/4 (24MHz)
4.3.3 Configuring the FLL with the RTC oscillator as a reference
The MCG can generate all the system clocks using the FLL with the RTC oscillator being
used as the reference for it. This has the benefit that an accurate reference clock can be
used without the cost of additional external components in an application where the RTC
is already being used.
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MCG_C2 |= MCG_C2_IRCS_MASK; // set the IRCS bit to select the fast IRC
MCG_C1 = MCG_C1_CLKS(1) | MCG_C1_FRDIV(3) | MCG_C1_IREFS_MASK;
while (!(MCG_S & MCG_S_IREFST_MASK)){}
while (!(MCG_S & MCG_S_IRCST_MASK)){}
while (((MCG_S & MCG_S_CLKST_MASK) >> MCG_S_CLKST_SHIFT) != 0x1){}
MCG_C2 |= MCG_C2_LP_MASK; // set the LP bit to enter BLPI
SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0) | SIM_CLKDIV1_OUTDIV2(0)
MCG_C2 &= ~MCG_C2_LP_MASK; // clear the LP bit to exit BLPI
MCG_C1 = MCG_C1_CLKS(2) | MCG_C1_FRDIV(3);
while (!(MCG_S & MCG_S_OSCINIT_MASK)){}
while (MCG_S & MCG_S_IREFST_MASK){}
while (((MCG_S & MCG_S_CLKST_MASK) >> MCG_S_CLKST_SHIFT) != 0x2){}
MCG_C5 = MCG_C5_PRDIV(1);
MCG_C6 = MCG_C6_PLLS_MASK;
while (!(MCG_S & MCG_S_PLLST_MASK)){}
while (!(MCG_S & MCG_S_LOCK_MASK)){}
SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0) | SIM_CLKDIV1_OUTDIV2(1)
MCG_C1 &= ~MCG_C1_CLKS_MASK;
while (((MCG_S & MCG_S_CLKST_MASK) >> MCG_S_CLKST_SHIFT) != 0x3){}
| SIM_CLKDIV1_OUTDIV3(0) | SIM_CLKDIV1_OUTDIV4(1);
| SIM_CLKDIV1_OUTDIV3(1) | SIM_CLKDIV1_OUTDIV4(3);
Kinetis Quick Reference User Guide, Rev. 0, 11/2010
// indicate switch to FLL output
Freescale Semiconductor