TWR-K60N512-KEIL Freescale Semiconductor, TWR-K60N512-KEIL Datasheet - Page 77

• Manufacturer Part Number: TWR-K60N512-KEIL
• Description: K60N512 Keil Tower Kit
• Manufacturer: Freescale Semiconductor
• Series: Kinetisr
• Type: MCUr

Specifications of TWR-K60N512-KEIL

• Rohs Compliant: YES
• Contents: 4 Boards, Documentation, DVD
• Peak Reflow Compatible (260 C): Yes
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Freescale Tower System, K60N512

Chapter 7 Enhanced Direct Memory Access (eDMA) Controller
7.5.2 Module configuration
To implement this example two eDMA channels are required: one to transfer the
command word and the other to transfer the result. The command transfer request
requires a 1 ms PIT trigger, and an always-on trigger. The DMA MUX must be
configured for PIT gated channel activation. Channel 1 is configured to perform this
transfer.
Channel 0 is used to transfer the AD result to RAM. This transfer is activated when the
AD result ready flag is asserted. The default channel arbitration gives channel 1 priority
over channel 0. This configuration ensures that the AD receives a command word every 1
ms. It could however cause results to be overwritten in the result register before they have
been moved by the eDMA, as the channel reading the results does not have priority. The
setup can be changed to ensure every result is captured to give the channel reading the
results higher priority. The DMA MUX configuration for channels 0 and 1 is:
/* Configure DMAMux for Channel 0 */
DMAMUX_CHCONFIG0 = (0
| DMAMUX_ENABLE /* Enable routing of DMA request */
| DMAMUX_SOURCE(40)); /* Channel Activation Source: AD_A Result */
/* Configure DMAMux for Channel 1 */
DMAMUX_CHCONFIG1 = (0
| DMAMUX_ENABLE /* Enable routing of DMA request */
| DMAMUX_TRIG /* Trigger Mode: Periodic */
| DMAMUX_SOURCE(54)); /* Channel Activation Source: AD_A Command */
Channel 1 is configured to use a periodic trigger ― PIT1. The PIT1 module must be
enabled and configured for the desired time interval.
The command data of the AD module must be prepared according to the definition of the
AD command register before starting the DMA transfer (enable PIT1). Each channel in
this example transfers data to or from the static-address, 32-bit wide command or result
register, respectively. Therefore, it is necessary to restore the address pointers in the TCD
when the major or minor transfer loop is complete. This example has no table of data to
transfer, making only a single minor loop necessary to complete a major loop. The source
and destination addresses are therefore restored on completion of the major loop. The
TCD configuration for channels 0 and 1 is:
/* Configure DMA Channel 0 TCD */
EDMAC_TCD0_W0 = EDMAC_SADDR(0x4003B010);/* Source Address = AD Result Register
EDMAC_TCD0_W1 = (0
| EDMAC_SMOD(0x0) /* Source Modulo, feature disabled */
| EDMAC_SSIZE(0x2) /* Source Size = 0x2 -> 32-bit transfers */
| EDMAC_DMOD(0x0) /* Destination Modulo, feature disabled */
| EDMAC_DSIZE(0x2) /* Destination Size = 0x2 -> 32-bit transfers */
| EDMAC_SOFF(0x0)); /* Source addr offset = 0x0, do not increment */
EDMAC_TCD0_W2 = EDMAC_NBYTES(0x4); /* Transfer 4 bytes per channel activation */
EDMAC_TCD0_W3 = EDMAC_SLAST(0x0); /* Do not adjust SADDR upon channel completion */
EDMAC_TCD0_W4 = EDMAC_DADDR(0x1FFF9000); /* Destination Address = 0x500, Ext RAM */
EDMAC_TCD0_W5 = (0
/*| EDMAC_CITER_E_LINK /* Do not set ELINK bit, no channel linking */
| EDMAC_CITER(0x1) /* Current Iter Count -> 1 "NBYTES" transfer */
| EDMAC_DOFF(0x0)); /* Destination addr offset = 0x0, no increment */
EDMAC_TCD0_W6 = EDMAC_DLAST(0x0); /* Do not adjust DADDR upon channel completion */
Kinetis Quick Reference User Guide, Rev. 0, 11/2010
Freescale Semiconductor
77