STM32W108HBU6 STMicroelectronics, STM32W108HBU6 Datasheet - Page 47

• Manufacturer Part Number: STM32W108HBU6
• Manufacturer: STMicroelectronics

Specifications of STM32W108HBU6

• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Processing Unit: Microprocessor
• Operating Supply Voltage (min): 1.18V
• Operating Supply Voltage (typ): 1.25V
• Operating Supply Voltage (max): 1.32V
• Package Type: VFQFPN EP
• Pin Count: 40
• Mounting: Surface Mount
• Rad Hardened: No
• Lead Free Status / Rohs Status: Supplier Unconfirmed

STM32W108CB, STM32W108HB
6.5
6.5.1
31
15
30
14
Bits [15:0] SLEEP_COMP_B_L (S/W name: SLEEPTMR_CMPBL_FIELD):
Sleep timer compare B low register (SLEEPTMR_CMPBL)
Address:
Reset value:
Power management
The STM32W108's power management system is designed to achieve the lowest deep
sleep current consumption possible while still providing flexible wakeup sources, timer
activity, and debugger operation. The STM32W108 has four main sleep modes:
●
●
●
●
Wake sources
When in deep sleep the STM32W108 can be returned to the running state in a number of
ways, and the wake sources are split depending on deep sleep 1 or deep sleep 2.
29
13
Idle Sleep: Puts the CPU into an idle state where execution is suspended until any
interrupt occurs. All power domains remain fully powered and nothing is reset.
Deep Sleep 1: The primary deep sleep state. In this state, the core power domain is
fully powered down and the sleep timer is active
Deep Sleep 2: The same as Deep Sleep 1 except that the sleep timer is inactive to
save power. In this mode the sleep timer cannot wakeup the STM32W108.
Deep Sleep 0 (also known as Emulated Deep Sleep): The chip emulates a true deep
sleep without powering down the core domain. Instead, the core domain remains
powered and all peripherals except the system debug components (ITM, DWT, FPB,
NVIC) are held in reset. The purpose of this sleep state is to allow STM32W108
software to perform a deep sleep cycle while maintaining debug configuration such as
breakpoints.
Sleep timer compare B low value [15:0].
Writing to this register puts value in hold register until a write to the SLEEPTMR_CMPBH
register.
Can only be changed when the ENABLE bit (bit 11 of SLEEP_CONFIG register) is set to ‘0’.
If changed when the ENABLE bit is set to ‘1’, a spurious interrupt may be generated.
Therefore it is recommended to disable interrupts before changing this register.
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12
27
11
0x4000 6024
0x0000 FFFF
26
10
25
9
Doc ID 16252 Rev 7
SLEEP_COMP_B_L
24
8
Reserved
rw
23
7
22
6
21
5
20
4
19
3
System modules
18
2
17
1
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16
0