LAN9303MI-AKZE Standard Microsystems (SMSC), LAN9303MI-AKZE Datasheet - Page 31

• Manufacturer Part Number: LAN9303MI-AKZE
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LAN9303MI-AKZE

• Lead Free Status / Rohs Status: Compliant

Small Form Factor Three Port 10/100 Managed Ethernet Switch with Dual MII/RMII/Turbo MII
Datasheet
SMSC LAN9303M/LAN9303Mi
PINS
PINS
NUM
NUM
1
1
1
Port 0 MII Input
Carrier Sense
Port 1 MII
Port 1 MII
Note 3.4
Note 3.5
Duplex
NAME
NAME
Data 3
Configuration strap pins are identified by an underlined symbol name. Configuration strap
values are latched on power-on reset or nRST de-assertion. Each port has configuration
straps that control its operation. Additional strap pins, which share functionality with the
GPIO/LED pins, are described in
by values from the EEPROM Loader. Please refer to
on page 51
An external supplemental pull-up may be needed, depending upon the input current
loading of the external MAC/PHY device.
P1_DUPLEX
SYMBOL
SYMBOL
P0_IND3
P1_CRS
Table 3.4 Port 1 MII/RMII Pins (continued)
for further information.
Table 3.5 Port 0 MII/RMII Pins
DATASHEET
BUFFER
BUFFER
TYPE
TYPE
(PD)
(PD)
(PU)
(PU)
(PU)
(PD)
(PD)
O8
IS
IS
IS
IS
IS
-
-
31
Table
MII MAC Mode: This pin is an input from the
external PHY indicating a network carrier.
MII PHY Mode: This pin is an output to the external
MAC indicating a network carrier. The output driver
is disabled when the
MII Basic Control Register
(P1_MII_BASIC_CONTROL).
RMII PHY Mode: This pin is not used.
Internal PHY Mode: This pin is not used.
MII MAC Mode: This pin can be changed at any
time (live value) and can be overridden by enabling
the
Control Register
typically tied to the duplex indication from the
external PHY. Please refer to the definition of the
DUPLEX_POL_1
MII PHY and RMII PHY Modes: This pin sets the
default of the
Basic Control Register
(P1_MII_BASIC_CONTROL)
high or low as needed. The pull-up is enabled.
Please refer to the definition of the
DUPLEX_POL_1
Internal PHY Mode: This pin is not used.
MII MAC Mode: This pin is the receive data 3 bit
from the external PHY to the switch.
MII PHY Mode: This pin is the transmit data 3 bit
from the external MAC to the switch. The pull-down
and input buffer are disabled when the
(VPHY_ISO)
Control Register
RMII PHY Mode: This pin is not used.
3.6. Some configuration straps can be overridden
Manual Duplex
bit is set in the
Duplex Mode
Section 4.2.4, "Configuration Straps,"
(P1_MII_BASIC_CONTROL). It is
(VPHY_BASIC_CTRL).
DESCRIPTION
DESCRIPTION
strap for further details.
strap for further details.
bit in the
Isolate
bit in the
bit is set in the
Port 1 MII Basic
Virtual PHY Basic
and is typically tied
Revision 1.4 (07-07-10)
Port 1 MII
Isolate
Port 1